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110 条记录 (耗时 0.032 秒)

    Schottky diode employing recesses for elements of junction barrier array
    6.
    发明授权
    Schottky diode employing recesses for elements of junction barrier array 有权
    肖特基二极管采用连接屏障阵列元件的凹槽

    公开(公告)号：US08664665B2

    公开(公告)日：2014-03-04

    申请号：US13229752

    申请日：2011-09-11

    申请人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

    发明人： Jason Patrick Henning ,  Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal ,  John Williams Palmour ,  Scott Allen

    IPC分类号： H01L29/15

    CPC分类号： H01L29/872 ,  H01L29/0619 ,  H01L29/1608 ,  H01L29/66143 ,  H01L2224/02166 ,  H01L2924/13055 ,  H01L2924/00

    摘要： The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the substrate. A junction barrier array is provided in the drift layer just below the Schottky layer. The elements of the junction barrier array are generally doped regions in the drift layer. To increase the depth of these doped regions, individual recesses may be formed in the surface of the drift layer where the elements of the junction barrier array are to be formed. Once the recesses are formed in the drift layer, areas about and at the bottom of the recesses are doped to form the respective elements of the junction barrier array.

    摘要翻译： 本发明一般涉及一种肖特基二极管，其具有衬底，设置在衬底上的漂移层以及设置在衬底的有源区上的肖特基层。 在位于肖特基层正下方的漂移层中提供了结屏障阵列。 结势垒阵列的元件通常是漂移层中的掺杂区域。 为了增加这些掺杂区域的深度，可以在要形成结屏障阵列的元件的漂移层的表面中形成单独的凹槽。 一旦凹陷形成在漂移层中，则凹部周围和底部的区域被掺杂以形成连接屏障阵列的相应元件。

    SiC devices with high blocking voltage terminated by a negative bevel
    9.
    发明授权
    SiC devices with high blocking voltage terminated by a negative bevel 有权
    具有高阻断电压的SiC器件由负斜角端接

    公开(公告)号：US09337268B2

    公开(公告)日：2016-05-10

    申请号：US13108366

    申请日：2011-05-16

    申请人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    发明人： Qingchun Zhang ,  Craig Capell ,  Anant Agarwal ,  Sei-Hyung Ryu

    IPC分类号： H01L29/06 ,  H01L29/10 ,  H01L29/36 ,  H01L29/732 ,  H01L29/739 ,  H01L29/74 ,  H01L29/78 ,  H01L29/861 ,  H01L29/16

    CPC分类号： H01L29/7813 ,  H01L21/0465 ,  H01L29/0615 ,  H01L29/0661 ,  H01L29/1004 ,  H01L29/1016 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/36 ,  H01L29/732 ,  H01L29/7397 ,  H01L29/74 ,  H01L29/861

    摘要： A negative bevel edge termination for a Silicon Carbide (SiC) semiconductor device is disclosed. In one embodiment, the negative bevel edge termination includes multiple steps that approximate a smooth negative bevel edge termination at a desired slope. More specifically, in one embodiment, the negative bevel edge termination includes at least five steps, at least ten steps, or at least 15 steps. The desired slope is, in one embodiment, less than or equal to fifteen degrees. In one embodiment, the negative bevel edge termination results in a blocking voltage for the semiconductor device of at least 10 kilovolts (kV) or at least 12 kV. The semiconductor device is preferably, but not necessarily, a thyristor such as a power thyristor, a Bipolar Junction Transistor (BJT), an Insulated Gate Bipolar Transistor (IGBT), a U-channel Metal-Oxide-Semiconductor Field Effect Transistor (UMOSFET), or a PIN diode.

    摘要翻译： 公开了一种用于碳化硅（SiC）半导体器件的负斜面边缘终端。 在一个实施例中，负斜边缘终端包括以期望的斜率近似平滑负斜面边缘终止的多个步骤。 更具体地，在一个实施例中，负斜边缘终止包括至少五个步骤，至少十个步骤或至少15个步骤。 在一个实施例中，期望的斜率小于或等于十五度。 在一个实施例中，负斜边缘终止导致半导体器件的阻挡电压为至少10千伏（kV）或至少12kV。 半导体器件优选但不一定是晶闸管，例如功率晶闸管，双极结晶体管（BJT），绝缘栅双极晶体管（IGBT），U沟道金属氧化物半导体场效应晶体管（UMOSFET） 或PIN二极管。

    Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same
    10.
    发明授权
    Semiconductor devices including Schottky diodes having doped regions arranged as islands and methods of fabricating same 有权
    包括具有排列成岛的掺杂区域的肖特基二极管的半导体器件及其制造方法

    公开(公告)号：US08330244B2

    公开(公告)日：2012-12-11

    申请号：US12492670

    申请日：2009-06-26

    申请人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

    发明人： Qingchun Zhang ,  Sei-Hyung Ryu ,  Anant Agarwal

    IPC分类号： H01L27/095 ,  H01L29/47 ,  H01L29/812 ,  H01L31/07

    CPC分类号： H01L29/0619 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/872

    摘要： A semiconductor device according to some embodiments includes a semiconductor layer having a first conductivity type and a surface in which an active region of the semiconductor device is defined. A plurality of spaced apart first doped regions are arranged within the active region. The plurality of first doped regions have a second conductivity type that is opposite the first conductivity type, have a first dopant concentration, and define a plurality of exposed portions of the semiconductor layer within the active region. The plurality of first doped regions are arranged as islands in the semiconductor layer. A second doped region in the semiconductor layer has the second conductivity type and has a second dopant concentration that is greater than the first dopant concentration.

    摘要翻译： 根据一些实施例的半导体器件包括具有第一导电类型的半导体层和限定半导体器件的有源区的表面。 多个间隔开的第一掺杂区域被布置在有源区域内。 多个第一掺杂区域具有与第一导电类型相反的第二导电类型，具有第一掺杂剂浓度，并且在有源区内限定半导体层的多个暴露部分。 多个第一掺杂区域在半导体层中被布置为岛状。 半导体层中的第二掺杂区域具有第二导电类型并且具有大于第一掺杂剂浓度的第二掺杂剂浓度。