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    Deuterium reservoirs and ingress paths
    1.
    发明授权
    Deuterium reservoirs and ingress paths 失效
    氘池和入口路径

    公开(公告)号：US06770501B2

    公开(公告)日：2004-08-03

    申请号：US10277835

    申请日：2002-10-23

    申请人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

    发明人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

    IPC分类号： H01L213205

    CPC分类号： H01L21/76224 ,  H01L21/3003 ,  H01L21/823481

    摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.

    摘要翻译： 半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。 板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。 氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。 后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此 允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。

    Deuterium reservoirs and ingress paths
    2.
    发明授权
    Deuterium reservoirs and ingress paths 有权
    氘池和入口路径

    公开(公告)号：US06521977B1

    公开(公告)日：2003-02-18

    申请号：US09489277

    申请日：2000-01-21

    申请人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

    发明人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

    IPC分类号： H01L2358

    CPC分类号： H01L21/76224 ,  H01L21/3003 ,  H01L21/823481

    摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.

    摘要翻译： 半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。 板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。 氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。 后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此 允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。

    FinFET WITH THIN GATE DIELECTRIC LAYER
    5.
    发明申请
    FinFET WITH THIN GATE DIELECTRIC LAYER 有权
    具有薄栅介质层的FinFET

    公开(公告)号：US20110175163A1

    公开(公告)日：2011-07-21

    申请号：US12688347

    申请日：2010-01-15

    申请人： Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

    发明人： Eduard A. Cartier ,  Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

    IPC分类号： H01L29/06 ,  H01L21/762

    CPC分类号： H01L29/785 ,  H01L29/66795

    摘要： A semiconductor device is provided that in one embodiment includes at least one semiconductor fin structure atop a dielectric surface, the semiconductor fin structure including a channel region of a first conductivity type and source and drain regions of a second conductivity type, in which the source and drain regions are present at opposing ends of the semiconductor fin structure. A high-k gate dielectric layer having a thickness ranging from 1.0 nm to 5.0 nm is in direct contact with the channel of the semiconductor fin structure. At least one gate conductor layer is in direct contact with the high-k gate dielectric layer. A method of forming the aforementioned device is also provided.

    摘要翻译： 提供了一种半导体器件，其在一个实施例中包括在电介质表面上方的至少一个半导体鳍结构，所述半导体鳍结构包括第一导电类型的沟道区和第二导电类型的源区和漏区， 漏区存在于半导体鳍结构的相对端。 具有1.0nm至5.0nm厚度的高k栅介质层与半导体鳍结构的沟道直接接触。 至少一个栅极导体层与高k栅极电介质层直接接触。 还提供了一种形成上述装置的方法。