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    SELECTIVE NITRIDATION OF GATE OXIDES
    1.
    发明申请
    SELECTIVE NITRIDATION OF GATE OXIDES 失效
    选择性硝化氮氧化物

    公开(公告)号：US20060281265A1

    公开(公告)日：2006-12-14

    申请号：US11465030

    申请日：2006-08-16

    申请人： Jay BURNHAM ,  John ELLIS-MONAGHAN ,  James NAKOS ,  James QUINLIVAN

    发明人： Jay BURNHAM ,  John ELLIS-MONAGHAN ,  James NAKOS ,  James QUINLIVAN

    IPC分类号： H01L21/336

    CPC分类号： H01L21/823857

    摘要： A method of fabricating a semiconductor structure. The method includes forming a first feature of a first active device and a second feature of a second active device, introducing a first amount of nitrogen into the first feature of the first active device, and introducing a second amount of nitrogen into the second feature of the second active device, the second amount of nitrogen being different from the first amount of nitrogen.

    摘要翻译： 一种制造半导体结构的方法。 该方法包括形成第一有源器件的第一特征和第二有源器件的第二特征，将第一量的氮引入第一有源器件的第一特征中，并将第二量的氮引入到第二有源器件的第二特征中 第二活性装置，第二氮量不同于第一氮量。

    SELECTIVE NITRIDATION OF GATE OXIDES
    6.
    发明申请
    SELECTIVE NITRIDATION OF GATE OXIDES 有权
    选择性硝化氮氧化物

    公开(公告)号：US20050164444A1

    公开(公告)日：2005-07-28

    申请号：US10707897

    申请日：2004-01-22

    申请人： Jay Burnham ,  John Ellis-Monaghan ,  James Nakos ,  James Quinlivan

    发明人： Jay Burnham ,  John Ellis-Monaghan ,  James Nakos ,  James Quinlivan

    IPC分类号： H01L27/092 ,  H01L21/318 ,  H01L21/8238 ,  H01L29/78

    CPC分类号： H01L21/823857

    摘要： A semiconductor structure includes thin gate dielectrics that have been selectively nitrogen enriched. The amount of nitrogen introduced is sufficient to reduce or prevent gate leakage and dopant penetration, without appreciably degrading device performance. A lower concentration of nitrogen is introduced into pFET gate dielectrics than into nFET gate dielectrics. Nitridation may be accomplished selectively by various techniques, including rapid thermal nitridation (RTN), furnace nitridation, remote plasma nitridation (RPN), decoupled plasma nitridation (DPN), well implantation and/or polysilicon implantation.

    摘要翻译： 半导体结构包括已经选择性地富氮的薄栅极电介质。 引入的氮气量足以减少或防止栅极泄漏和掺杂剂渗透，而不会明显降低器件性能。 较低浓度的氮被引入到pFET栅极电介质中，而不是nFET栅极电介质。 氮化可以通过各种技术选择性地完成，包括快速热氮化（RTN），炉氮化，远程等离子体氮化（RPN），去耦等离子体氮化（DPN），阱注入和/或多晶硅注入。

    Deuterium reservoirs and ingress paths
    9.
    发明授权
    Deuterium reservoirs and ingress paths 失效
    氘池和入口路径

    公开(公告)号：US06770501B2

    公开(公告)日：2004-08-03

    申请号：US10277835

    申请日：2002-10-23

    申请人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

    发明人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

    IPC分类号： H01L213205

    CPC分类号： H01L21/76224 ,  H01L21/3003 ,  H01L21/823481

    摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.

    摘要翻译： 半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。 板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。 氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。 后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此 允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。

    Deuterium reservoirs and ingress paths
    10.
    发明授权
    Deuterium reservoirs and ingress paths 有权
    氘池和入口路径

    公开(公告)号：US06521977B1

    公开(公告)日：2003-02-18

    申请号：US09489277

    申请日：2000-01-21

    申请人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

    发明人： Jay Burnham ,  Eduard A. Cartier ,  Thomas G. Ference ,  Steven W. Mittl ,  Anthony K. Stamper

    IPC分类号： H01L2358

    CPC分类号： H01L21/76224 ,  H01L21/3003 ,  H01L21/823481

    摘要： Semiconductor structures are provided with on-board deuterium reservoirs or with deuterium ingress paths which allow for diffusion of deuterium to semiconductor device regions for passivation purposes. The on-board deuterium reservoirs are in the form of plugs which extend through an insulating layer and a deuterium barrier layer to the semiconductor substrate, and are preferably positioned in contact with a shallow trench oxide which will allow diffusion of deuterium to the semiconductor devices. The deuterium ingress paths extend through thin film layers from the top or through the silicon substrate. The latter include shallow trench isolations formed in a semiconductor substrate which are adjacent and connected to semiconductor devices formed in the semiconductor substrate, and where the back portion of the semiconductor substrate has been polished or ground down to the bottom of the shallow trench isolation, thereby allowing deuterium, during an anneal, to diffuse from the back through the shallow trench isolation to the semiconductor devices in the semiconductor substrate.

    摘要翻译： 半导体结构设置有板上氘储层或氘入口路径，其允许氘扩散到半导体器件区域用于钝化目的。 板上氘储存器是插塞的形式，其延伸穿过绝缘层和氘屏障层到半导体衬底，并且优选地定位成与允许氘扩散到半导体器件的浅沟槽氧化物接触。 氘入口路径从顶部或穿过硅衬底延伸穿过薄膜层。 后者包括形成在半导体衬底中的与沟道半导体衬底中形成的半导体器件相邻并连接的浅沟槽隔离，并且其中半导体衬底的后部已经被抛光或者被研磨到浅沟槽隔离的底部，由此 允许在退火期间的氘从后面通过浅沟槽隔离扩散到半导体衬底中的半导体器件。