公开(公告)号：US06255178B1

公开(公告)日：2001-07-03

申请号：US09368767

申请日：1999-08-05

申请人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L21336

CPC分类号： H01L29/66492 ,  G03F7/095 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659

摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

摘要翻译： 本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。 特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。 升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。 用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。 然后通过生长硅将源极区和漏极区连接到衬底。 因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

公开(公告)号：US06420766B1

公开(公告)日：2002-07-16

申请号：US09368843

申请日：1999-08-05

申请人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L2976

CPC分类号： H01L29/66492 ,  G03F7/095 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/26586 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659

摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

摘要翻译： 本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。 特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。 升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。 用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。 然后通过生长硅将源极区和漏极区连接到衬底。 因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

公开(公告)号：US6100013A

公开(公告)日：2000-08-08

申请号：US71207

申请日：1998-05-01

申请人： Jeffery S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffery S. Brown ,  James S. Dunn ,  Steven J. Holmes ,  David V. Horak ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L29/78 ,  G03F7/095 ,  G03F7/38 ,  H01L21/027 ,  H01L21/265 ,  H01L21/311 ,  H01L21/336 ,  G03F7/20

CPC分类号： H01L29/66492 ,  G03F7/38 ,  H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/6659 ,  G03F7/095 ,  H01L21/26586

摘要： The preferred embodiment of the present invention provides a transistor structure and method for fabricating the same that overcomes the disadvantages of the prior art. In particular, the preferred structure and method results in lower leakage and junction capacitance by using raised source and drains which are partially isolated from the substrate by a dielectric layer. The raised source and drains are preferably fabricated from the same material layer used to form the transistor gate. The preferred method for fabricating the transistor uses hybrid resist to accurately pattern the gate material layer into regions for the gate, the source and the drain. The source and drain regions are then connected to the substrate by growing silicon. The preferred method thus results in an improved transistor structure while not requiring excessive fabrication steps.

摘要翻译： 本发明的优选实施例提供了克服现有技术的缺点的晶体管结构及其制造方法。 特别地，优选的结构和方法通过使用通过电介质层与衬底部分隔离的凸起源极和漏极导致较低的漏电和结电容。 升高的源极和漏极优选由用于形成晶体管栅极的相同材料层制成。 用于制造晶体管的优选方法使用混合抗蚀剂将栅极材料层精确地图案化成用于栅极，源极和漏极的区域。 然后通过生长硅将源极区和漏极区连接到衬底。 因此，优选的方法导致改进的晶体管结构，而不需要过多的制造步骤。

公开(公告)号：US5939767A

公开(公告)日：1999-08-17

申请号：US052512

申请日：1998-03-31

申请人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/866 ,  H01L29/00 ,  H01L29/861 ,  H01L31/107

CPC分类号： H01L27/0255 ,  H01L21/8238

摘要： According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.

摘要翻译： 根据本发明，公开了一种用于CMOS处理中的埋二极管形成的改进方法。 使用混合光刻胶工艺，使用两步光刻掩模工艺创建自对准齐纳二极管。 由于本发明公开的方法仅使用p阱和n-阱掩模来产生齐纳二极管，所以减小了光刻对准问题，并且可以在亚微米级产生齐纳二极管。

公开(公告)号：US06218704B1

公开(公告)日：2001-04-17

申请号：US08851973

申请日：1997-05-07

申请人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L2362

CPC分类号： H01L27/0288 ,  H01L27/0255 ,  H01L29/1083 ,  H01L2924/0002 ,  H01L2924/00

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the robustness of electrostatic discharge (ESD) protection devices by reducing the temperature gradient caused by ESD pulses and reducing the likelihood of thermal runaway caused by large ESD pulses. The preferred embodiment forms implants under the trench isolation structures in the ESD devices. The implants reduce the current-caused heating that can lead to thermal runaway, and thus improve the robustness of the ESD protection device. In the preferred embodiment, the implants are formed using hybrid resist. The hybrid resist provides a method to form that implants that does not require additional masking steps or other excessive processing. Additionally, the hybrid resist provides implants that are self aligned with the well regions.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过降低ESD脉冲引起的温度梯度并降低由于静电放电（ESD）保护装置引起的热失控的可能性而增加静电放电（ESD）保护装置的鲁棒性的装置和方法 大ESD脉冲。 优选实施例在ESD器件中的沟槽隔离结构之下形成植入物。 植入物减少导致热失控的电流引起的加热，从而提高ESD保护装置的鲁棒性。 在优选实施例中，使用混合抗蚀剂形成植入物。 混合抗蚀剂提供了形成不需要额外掩蔽步骤或其它过量处理的植入物的方法。 此外，混合抗蚀剂提供与阱区自对准的植入物。

公开(公告)号：US06232639B1

公开(公告)日：2001-05-15

申请号：US09107900

申请日：1998-06-30

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L2976

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。 优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。 植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。 这降低了CMOS器件闭锁的倾向。 优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。 此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

公开(公告)号：US6033949A

公开(公告)日：2000-03-07

申请号：US107813

申请日：1998-06-30

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。 优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。 植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。 这降低了CMOS器件闭锁的倾向。 优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。 此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

公开(公告)号：US5882967A

公开(公告)日：1999-03-16

申请号：US852850

申请日：1997-05-07

申请人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Steven J. Holmes ,  Robert K. Leidy ,  Steven H. Voldman

IPC分类号： H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L29/866 ,  H01L21/8234

CPC分类号： H01L27/0255 ,  H01L21/8238

摘要： According to the present invention, an improved method for buried diode formation in CMOS processing is disclosed. Using a hybrid photoresist process, a self-aligning Zener diode is created using a two-step photolithography mask process. Since the process disclosed in the invention uses only the p-well and the n-well masks to create the Zener diode, photolithography alignment problems are reduced and Zener diodes can be create at the sub-micron scale.

摘要翻译： 根据本发明，公开了一种用于CMOS处理中的埋二极管形成的改进方法。 使用混合光刻胶工艺，使用两步光刻掩模工艺创建自对准齐纳二极管。 由于本发明公开的方法仅使用p阱和n-阱掩模来产生齐纳二极管，所以减小了光刻对准问题，并且可以在亚微米级产生齐纳二极管。

公开(公告)号：US5861330A

公开(公告)日：1999-01-19

申请号：US852466

申请日：1997-05-07

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

公开(公告)号：US06429045B1

公开(公告)日：2002-08-06

申请号：US09779215

申请日：2001-02-07

申请人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

发明人： Toshiharu Furukawa ,  Mark C. Hakey ,  Steven J. Holmes ,  David V. Horak ,  H. Bernhard Pogge ,  Edmund J. Sprogis ,  Steven H. Voldman

IPC分类号： H01L2144

CPC分类号： H01L29/0657 ,  H01L21/563 ,  H01L23/544 ,  H01L24/81 ,  H01L25/0655 ,  H01L2223/54473 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/81005 ,  H01L2224/81007 ,  H01L2224/81136 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/10158 ,  Y10S438/928 ,  H01L2924/00012

摘要： A technique for fabricating precision aligned macros (PAMs) with reduced risk of electrostatic discharge damage and thermal damage. An electrical and thermal contact is provided through the back of the individual chips to a supporting silicon substrate. A conductive seed layer for electroplating is formed on a support substrate. A dielectric (preferably, a thermid) layer is formed on the seed layer. Vias are formed in the thermid layer and metal contacts are formed in the vias. The front faces of two or more chips are bonded onto the top surface of an alignment substrate, and the chips are aligned to the alignment substrate. The back faces of the chips are bonded to the metal contacts and thermid layer with heat and pressure. The alignment substrate is removed. The front faces of the chips are planarized. Finally, interconnect wiring is formed over the chips and thermid layer.

摘要翻译： 一种制造精密对准宏（PAM）的技术，降低了静电放电损伤和热损伤的风险。 通过单个芯片的背面提供电接触和热接触到支撑硅衬底。 用于电镀的导电种子层形成在支撑衬底上。 在种子层上形成电介质（优选为热）层。 通孔形成在热层中，金属触点形成在通孔中。 将两个以上的芯片的正面接合在取向基板的顶面上，将芯片与取向基板对准。 芯片的背面通过热和压力结合到金属触点和热层。 取出对准基板。 芯片的正面平面化。 最后，在芯片和热层上形成互连布线。