公开(公告)号：US06232639B1

公开(公告)日：2001-05-15

申请号：US09107900

申请日：1998-06-30

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L2976

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。 优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。 植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。 这降低了CMOS器件闭锁的倾向。 优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。 此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

公开(公告)号：US6033949A

公开(公告)日：2000-03-07

申请号：US107813

申请日：1998-06-30

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

摘要翻译： 本发明的优选实施例克服了现有技术的限制，并且提供了一种通过在阱边缘处形成植入物来增加CMOS器件的闩锁抗扰度的装置和方法。 优选的方法使用混合抗蚀剂在N阱和/或P阱的边缘形成这些植入物。 植入物减少了寄生晶体管中少数载流子的寿命，从而降低了寄生晶体管的增益。 这降低了CMOS器件闭锁的倾向。 优选实施例方法允许形成这些植入物，而不需要比现有技术方法更多的掩蔽步骤。 此外，用于形成植入物的优选方法导致与孔的边缘自对准的植入物。

公开(公告)号：US5861330A

公开(公告)日：1999-01-19

申请号：US852466

申请日：1997-05-07

申请人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

发明人： Faye D. Baker ,  Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven J. Holmes ,  Robert K. Leidy ,  Edward J. Nowak ,  Steven H. Voldman

IPC分类号： H01L21/761 ,  G03F7/004 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092

CPC分类号： H01L21/823878 ,  H01L27/0921 ,  Y10S148/137

摘要： The preferred embodiment of the present invention overcomes the limitations of the prior art and provides a device and method to increase the latch-up immunity of CMOS devices by forming implants at the well edges. The preferred method uses hybrid resist to form these implants at the edges of the N-wells and/or P-wells. The implants reduce the lifetime of minority carriers in the parasitic transistor, and hence reduce the gain of the parasitic transistor. This reduces the propensity of the CMOS device to latch-up. The preferred embodiment method allows these implants to be formed without requiring additional masking steps over prior art methods. Furthermore, the preferred method for forming the implants results in implants that are self aligned to the edges of the wells.

公开(公告)号：US06232163B1

公开(公告)日：2001-05-15

申请号：US09362549

申请日：1999-07-28

申请人： Steven H. Voldman ,  Robert J. Gauthier, Jr. ,  Jeffrey S. Brown

发明人： Steven H. Voldman ,  Robert J. Gauthier, Jr. ,  Jeffrey S. Brown

IPC分类号： H01L218238

CPC分类号： H01L27/0811 ,  H01L29/7391 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method may be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.

摘要翻译： 用于混合电压，混合信号和模拟/数字应用的高耐压二极管结构。 优选的硅二极管包括在半导体（硅）层或主体上的至少一个电介质膜层上的多晶硅栅极结构。 阱体或植入区域形成在SOI半导体衬底或SOI晶片的表面硅层中。 施加到多晶硅栅极膜的电压，电耗电，降低电介质膜两端的电压。 本征多晶硅膜可以是反掺杂的，注入低掺杂注入，注入低掺杂源/漏注入，或者与低掺杂的MOSFET LDD或延伸注入。 或者，当限定耗尽多晶硅栅极硅二极管以形成低串联电阻二极管植入物时，可以在栅极结构上形成块掩模，防止膜过度掺杂。 可选地，可以使用混合光致抗蚀剂方法在硅中形成更高掺杂的边缘注入，以减少二极管串联电阻而不使用块掩模。

公开(公告)号：US6034388A

公开(公告)日：2000-03-07

申请号：US79846

申请日：1998-05-15

申请人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

IPC分类号： H01L21/334 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/12 ,  H01L29/94 ,  H01L29/76

CPC分类号： H01L29/66181 ,  H01L21/76237 ,  H01L21/76264 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/94 ,  H01L21/76283 ,  Y10S257/907

摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.

摘要翻译： 一种包括半导体衬底的电路元件。 第一导电类型的阱区形成在衬底的表面中。 在基板上形成电介质膜。 在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。 栅极导体由多晶硅膜形成。 栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 在栅极导体的每一侧上形成多晶硅边缘隔离物。 第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。 多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。 第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。 应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。

公开(公告)号：US6100143A

公开(公告)日：2000-08-08

申请号：US267239

申请日：1999-03-12

申请人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/6659 ,  H01L21/28105 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/4238 ,  H01L29/4983 ,  Y10S438/919

摘要： A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions.The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance. The structure has improved edge dielectric breakdown and lower MOSFET gate-induced drain leakage (GIDL). This structure is intended for analog applications, mixed voltage tolerant circuits and electrostatic (ESD) networks.

摘要翻译： 具有减小的拐角设备问题的场效应晶体管包括形成在衬底中的源极和漏极区域，源极和漏极区域之间的沟道区域，邻近源极，沟道和漏极区域的衬底中的隔离区域; 以及在沟道区域上具有栅极掺杂剂并由栅极电介质分离的栅极。 隔离区域定义了通道与隔离区域之间的接口的拐角区域。 栅极包括耗尽栅极掺杂剂的区域，并且至少与沟道区域和隔离区域重叠，使得栅极导体层的耗尽部分之下的沟道拐角区域的电压阈值与角区域之间的沟道区域相比增加 。 MOSFET栅极“拐角”上掺杂浓度降低的场效应晶体管具有改善的边缘电压容差。 该结构具有改善的边缘电介质击穿和较低的MOSFET栅极引起的漏极泄漏（GIDL）。 该结构适用于模拟应用，混合耐压电路和静电（ESD）网络。

公开(公告)号：US06429066B1

公开(公告)日：2002-08-06

申请号：US09465097

申请日：1999-12-16

申请人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

IPC分类号： H01L218242

CPC分类号： H01L29/66181 ,  H01L21/76237 ,  H01L21/76264 ,  H01L21/76283 ,  H01L21/823842 ,  H01L21/82385 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/94 ,  Y10S257/907

摘要： A circuit element comprising a semiconductor substrate. A well region of a first conductivity type is formed in a surface of the substrate. A dielectric film is formed on the substrate. A gate conductor of the first conductivity type is formed on the dielectric film over the well region of the substrate. The gate conductor is formed of a polycrystalline silicon film. The gate conductor has an impurity concentration substantially lower than a standard impurity concentration for the gate conductor of an MOS device. A polycrystalline silicon edge spacer is formed on each side of the gate conductor. A first pair of first conductivity type impurity diffusion regions are formed adjacent to the polycrystalline silicon edge spacers. The polycrystalline silicon film and edge spacers lie on a portion of the substrate between the first pair of first conductivity type impurity diffusion regions. The first pair of first conductivity type impurity diffusion regions have an impurity concentration substantially lower than the standard impurity concentration for the gate conductor of an MOS device. The gate conductor and the first pair of first conductivity type impurity diffusion regions may be formed by a single implantation step. Applications include ESD protection, analog applications, peripheral input/output circuitry, decoupling capacitors, and resistor ballasting.

摘要翻译： 一种包括半导体衬底的电路元件。 第一导电类型的阱区形成在衬底的表面中。 在基板上形成电介质膜。 在衬底的阱区上的电介质膜上形成第一导电类型的栅极导体。 栅极导体由多晶硅膜形成。 栅极导体的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 在栅极导体的每一侧上形成多晶硅边缘隔离物。 第一对第一导电型杂质扩散区形成在与多晶硅边缘隔离物相邻的位置。 多晶硅膜和边缘隔离物位于第一对第一导电型杂质扩散区之间的衬底的一部分上。 第一对第一导电型杂质扩散区的杂质浓度基本上低于MOS器件的栅极导体的标准杂质浓度。 可以通过单个注入步骤形成栅极导体和第一对第一导电型杂质扩散区。 应用包括ESD保护，模拟应用，外围输入/输出电路，去耦电容和电阻镇流器。

公开(公告)号：US5998848A

公开(公告)日：1999-12-07

申请号：US157003

申请日：1998-09-18

申请人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

发明人： Jeffrey S. Brown ,  Robert J. Gauthier, Jr. ,  Steven H. Voldman

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC分类号： H01L29/6659 ,  H01L21/28105 ,  H01L21/28123 ,  H01L21/76224 ,  H01L29/4238 ,  H01L29/4983 ,  Y10S438/919

摘要： A field effect transistor with reduced corner device problems comprises source and drain regions formed in a substrate, a channel region between the source and drain regions, isolation regions in the substrate adjacent the source, channel and drain regions; and a gate having a gate dopant over the channel region and separated therefrom by a gate dielectric. The isolation regions define corner regions of the channel along interfaces between the channel and isolation regions. The gate includes regions depleted of the gate dopant and overlapping at least the channel region and the isolation regions, such that voltage thresholds of the channel corner regions beneath depleted portions of the gate conductor layer are increased compared to regions of the channel between the corner regions.The field effect transistor with reduced dopant concentration on the MOSFET gate "corner" has an improved edge voltage tolerance. The structure has improved edge dielectric breakdown and lower MOSFET gate-induced drain leakage (GIDL). This structure is intended for analog applications, mixed voltage tolerant circuits and electrostatic (ESD) networks.

摘要翻译： 具有减小的拐角设备问题的场效应晶体管包括形成在衬底中的源极和漏极区域，源极和漏极区域之间的沟道区域，邻近源极，沟道和漏极区域的衬底中的隔离区域; 以及在沟道区域上具有栅极掺杂剂并由栅极电介质分离的栅极。 隔离区域定义了通道与隔离区域之间的接口的拐角区域。 栅极包括耗尽栅极掺杂剂的区域，并且至少与沟道区域和隔离区域重叠，使得栅极导体层的耗尽部分之下的沟道拐角区域的电压阈值与角区域之间的沟道区域相比增加 。 MOSFET栅极“拐角”上掺杂浓度降低的场效应晶体管具有改善的边缘电压容差。 该结构具有改善的边缘电介质击穿和较低的MOSFET栅极引起的漏极泄漏（GIDL）。 该结构适用于模拟应用，混合耐压电路和静电（ESD）网络。

公开(公告)号：US6015993A

公开(公告)日：2000-01-18

申请号：US144386

申请日：1998-08-31

申请人： Steven H. Voldman ,  Robert J. Gauthier, Jr. ,  Jeffrey S. Brown

发明人： Steven H. Voldman ,  Robert J. Gauthier, Jr. ,  Jeffrey S. Brown

IPC分类号： H01L29/861 ,  H01L27/08 ,  H01L29/739 ,  H01L23/62 ,  H01L29/00 ,  H01L29/76

CPC分类号： H01L27/0811 ,  H01L29/7391 ,  H01L2924/0002

摘要： A high voltage tolerant diode structure for mixed-voltage, and mixed signal and analog/digital applications. The preferred silicon diode includes a polysilicon gate structure on at least one dielectric film layer on a semiconductor (silicon) layer or body. A well or an implanted area is formed in a bulk semiconductor substrate or in a surface silicon layer on an SOI wafer. Voltage applied to the polysilicon gate film, electrically depletes it, reducing voltage stress across the dielectric film. An intrinsic polysilicon film may be counter-doped, implanted with a low doped implantation, implanted with a low doped source/drain implant, or with a low doped MOSFET LDD or extension implant. Alternatively, a block mask may be formed over the gate structure when defining the depleted-polysilicon gate silicon diode to form low series resistance diode implants, preventing over-doping the film. Optionally, a hybrid photoresist method mey be used to form higher doped edge implants in the silicon to reduce diode series resistance without a block mask.

摘要翻译： 用于混合电压，混合信号和模拟/数字应用的高耐压二极管结构。 优选的硅二极管包括在半导体（硅）层或主体上的至少一个电介质膜层上的多晶硅栅极结构。 阱体或植入区域形成在SOI半导体衬底或SOI晶片的表面硅层中。 施加到多晶硅栅极膜的电压，电耗电，降低电介质膜两端的电压。 本征多晶硅膜可以是反掺杂的，注入低掺杂注入，注入低掺杂源/漏注入，或者与低掺杂的MOSFET LDD或延伸注入。 或者，当限定耗尽多晶硅栅极硅二极管以形成低串联电阻二极管植入物时，可以在栅极结构上形成块掩模，防止膜过度掺杂。 可选地，可以使用混合光刻胶方法在硅中形成更高掺杂的边缘注入，以减少二极管串联电阻而不使用块掩模。

公开(公告)号：US07473970B2

公开(公告)日：2009-01-06

申请号：US11481120

申请日：2006-07-05

申请人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

发明人： Wagdi W. Abadeer ,  Jeffrey S. Brown ,  David M. Fried ,  Robert J. Gauthier, Jr. ,  Edward J. Nowak ,  Jed H. Rankin ,  William R. Tonti

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L29/786 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/4908 ,  H01L29/78615

摘要： An integrated circuit chip and a semiconductor structure. The integrated circuit chip includes: a thick-body device containing a semiconductor mesa and a doped body contact; and a field effect transistor on a first sidewall of a semiconductor mesa, wherein the doped body contact is on a second sidewall of the semiconductor mesa, and wherein the semiconductor mesa is disposed between the field effect transistor and the doped body contact. The semiconductor structure includes: a buried oxide layer on a semiconductor wafer; a thin fin structure on the buried oxide layer, wherein the thin fin structure includes a first hard mask on a semiconductor fin, wherein the semiconductor fin is disposed between the first hard mask and a surface of the buried oxide layer; and a thick mesa structure on the buried oxide layer, and wherein the thick mesa structure includes a semiconductor mesa.

摘要翻译： 集成电路芯片和半导体结构。 集成电路芯片包括：包含半导体台面和掺杂体接触的厚体器件; 以及在半导体台面的第一侧壁上的场效应晶体管，其中所述掺杂体接触在所述半导体台面的第二侧壁上，并且其中所述半导体台面设置在所述场效应晶体管和所述掺杂体接触之间。 半导体结构包括：半导体晶片上的掩埋氧化物层; 在所述掩埋氧化物层上的薄翅片结构，其中所述薄翅片结构包括半导体鳍片上的第一硬掩模，其中所述半导体鳍片设置在所述第一硬掩模和所述掩埋氧化物层的表面之间; 以及在所述掩埋氧化物层上的厚的台面结构，并且其中所述厚的台面结构包括半导体台面。