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    VARIABLE RESISTANCE MEMORY DEVICE USING A CHANNEL-SHAPED VARIABLE RESISTANCE PATTERN
    1.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE USING A CHANNEL-SHAPED VARIABLE RESISTANCE PATTERN 审中-公开
    使用通道形变可变电阻图案的可变电阻存储器件

    公开(公告)号：US20100051896A1

    公开(公告)日：2010-03-04

    申请号：US12549887

    申请日：2009-08-28

    申请人： Jeonghee Park ,  Yongho Ha ,  Dohyung Kim ,  Joonsang Park ,  Hyeyoung Park ,  Hyun-Suk Kwon

    发明人： Jeonghee Park ,  Yongho Ha ,  Dohyung Kim ,  Joonsang Park ,  Hyeyoung Park ,  Hyun-Suk Kwon

    IPC分类号： H01L47/00

    CPC分类号： H01L27/24

    摘要： A variable resistance memory device includes a substrate and a plurality of spaced apart lower electrodes on the substrate. The device further includes a variable resistance material pattern comprising two vertically opposed wall members connected by a bottom member disposed on and electrically connected to at least one of the plurality of lower electrodes and an upper electrode on the variable resistance material pattern. An area of contact of the variable resistance material pattern with the at least one lower electrode may be rectangular, circular, ring-shaped, or arc-shaped. Fabrication methods are also described.

    摘要翻译： 可变电阻存储器件包括衬底和在衬底上的多个间隔开的下电极。 该装置还包括可变电阻材料图案，包括两个垂直相对的壁构件，该两个垂直相对的壁构件通过设置在多个下部电极中的至少一个上并与其电连接的底部构件和可变电阻材料图案上的上部电极连接。 可变电阻材料图案与至少一个下电极的接触区域可以是矩形，圆形，环形或弧形。 还描述了制造方法。

    Phase Changeable Memory Devices and Methods of Forming the Same
    3.
    发明申请
    Phase Changeable Memory Devices and Methods of Forming the Same 审中-公开
    相变存储器件及其形成方法

    公开(公告)号：US20110186798A1

    公开(公告)日：2011-08-04

    申请号：US13019822

    申请日：2011-02-02

    申请人： Hyun-Suk Kwon ,  Hyeyoung Park ,  Jeonghee Park ,  Gyuhwan Oh ,  Jinho Oh ,  Doo-Hwan Park

    发明人： Hyun-Suk Kwon ,  Hyeyoung Park ,  Jeonghee Park ,  Gyuhwan Oh ,  Jinho Oh ,  Doo-Hwan Park

    IPC分类号： H01L45/00

    CPC分类号： H01L45/144 ,  G11C13/0004 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/124 ,  H01L45/1683 ,  H01L45/1691

    摘要： Phase changeable memory devices are provided including a mold insulating layer on a substrate, the mold insulating layer defining an opening therein. A phase-change material layer is provided in the opening. The phase-change material includes an upper surface that is below a surface of the mold insulating layer. A first electrode is provided in the opening and on the phase-change material layer. A spacer is provided between a sidewall of the mold insulating layer and the phase-change material layer and the first electrode. The upper surface of the first electrode is coplanar with the surface of the mold insulating layer. Related methods are also provided.

    摘要翻译： 提供了相变存储器件，其包括在基底上的模具绝缘层，模具绝缘层在其中限定开口。 在开口中设置相变材料层。 相变材料包括在模具绝缘层的表面下方的上表面。 第一电极设置在开口和相变材料层上。 在模具绝缘层的侧壁和相变材料层和第一电极之间设置间隔件。 第一电极的上表面与模具绝缘层的表面共面。 还提供了相关方法。

    VARIABLE RESISTANCE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME
    4.
    发明申请
    VARIABLE RESISTANCE MEMORY DEVICE, METHOD OF FABRICATING THE SAME, AND MEMORY SYSTEM INCLUDING THE SAME 审中-公开
    可变电阻存储器件，其制造方法和包括其的存储器系统

    公开(公告)号：US20100124800A1

    公开(公告)日：2010-05-20

    申请号：US12617754

    申请日：2009-11-13

    申请人： Jeonghee Park ,  Sunglae Cho ,  Yongho Ha ,  Hyun-Suk Kwon

    发明人： Jeonghee Park ,  Sunglae Cho ,  Yongho Ha ,  Hyun-Suk Kwon

    IPC分类号： H01L21/06

    CPC分类号： H01L45/06 ,  H01L27/2463 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1683

    摘要： A method of fabricating a variable resistance memory device includes a plasma etching process to remove contaminants from variable resistance material that forms variable resistance elements of the device. Bottom electrodes are formed on a semiconductor substrate. Next, an interlayer dielectric layer having trenches that expose the bottom electrodes is formed on the substrate. Then a layer of variable resistance material is formed. The variable resistance material covers the interlayer dielectric layer and fills the trenches. The variable resistance material is then planarized down to at least the top surface of the interlayer dielectric layer, thereby leaving elements of the variable resistance material in the trenches. The variable resistance material in the trenches is etched to remove contaminants, produced as a result of the planarizing process, from atop the variable resistance material in the trenches. A top electrode is then formed on the variable resistance material.

    摘要翻译： 制造可变电阻存储器件的方法包括等离子体蚀刻工艺，以从形成该器件的可变电阻元件的可变电阻材料中除去污染物。 底电极形成在半导体衬底上。 接下来，在基板上形成具有露出底部电极的沟槽的层间电介质层。 然后形成一层可变电阻材料。 可变电阻材料覆盖层间电介质层并填充沟槽。 然后将可变电阻材料平坦化到至少层间电介质层的顶表面，从而将可变电阻材料的元件留在沟槽中。 蚀刻沟槽中的可变电阻材料，以从沟槽中的可变电阻材料的顶部去除作为平坦化处理的结果产生的污染物。 然后在可变电阻材料上形成顶部电极。