公开(公告)号：US20070283418A1

公开(公告)日：2007-12-06

申请号：US11344894

申请日：2006-02-01

申请人： Jihong Chen ,  Sam Hsu ,  Saeed Rajput

发明人： Jihong Chen ,  Sam Hsu ,  Saeed Rajput

IPC分类号： G06F7/04

CPC分类号： G06F21/31

摘要： A system for authenticating access to a data processing device or database is provided. The system includes a comparison module for comparing an attempt identifier with an account identifier, and a state-determining module for determining a state variable associated with at least one of the attempt identifier and the account identifier. The state-determining module determines the state variable by incrementing the state variable if the attempt identifier does not match the account identifier and if the state variable is less than a predetermined upper bound threshold, decrementing the state variable if the attempt identifier does match the account identifier and if the state variable is greater than a predetermined lower bound threshold, and authenticating the attempt identifier if the attempt identifier does match the account identifier and if the state variable equals the predetermined lower bound threshold.

摘要翻译： 提供了用于认证对数据处理设备或数据库的访问的系统。 该系统包括用于将尝试标识符与帐户标识符进行比较的比较模块，以及用于确定与至少一个尝试标识符和帐户标识符相关联的状态变量的状态确定模块。 状态确定模块如果尝试标识符与帐户标识符不匹配并且如果状态变量小于预定的上限阈值则通过递增状态变量来确定状态变量，如果尝试标识符与帐户匹配则递减状态变量 标识符，如果状态变量大于预定的下限阈值，并且如果尝试标识符与帐户标识符匹配并且状态变量等于预定下限阈值则认证尝试标识符。

公开(公告)号：US20130193559A1

公开(公告)日：2013-08-01

申请号：US13360144

申请日：2012-01-27

申请人： Jihong Chen

发明人： Jihong Chen

IPC分类号： H01L29/30

CPC分类号： H01L31/028 ,  C30B11/002 ,  C30B11/14 ,  H01L31/03682 ,  H01L31/182 ,  Y02E10/546 ,  Y02E10/547 ,  Y02P70/521

摘要： A cast silicon crystalline ingot comprises two major generally parallel surfaces, one of which is the front surface and the other of which is the back surface; a perimeter surface connecting the front surface and the back surface; and a bulk region between the front surface and the back surface; wherein the cast silicon crystalline ingot has no transverse dimension less than about five centimeters; the cast silicon crystalline ingot has a dislocation density of less than 1000 dislocations/cm2. Wafers sliced from the cast silicon crystalline ingot have solar cell efficiency of at least 17.5% and light induced degradation no greater than 0.2%.

摘要翻译： 铸造硅晶锭包括两个主要的大致平行的表面，其中一个是前表面，另一个是后表面; 连接前表面和后表面的周边表面; 以及前表面和后表面之间的主体区域; 其中所述铸造硅晶锭的横向尺寸不小于约5厘米; 铸硅晶锭的位错密度小于1000位错/ cm2。 从铸硅晶锭切片的晶片具有至少17.5％的太阳能电池效率和光诱导的降解不大于0.2％。

公开(公告)号：US07371648B2

公开(公告)日：2008-05-13

申请号：US11469512

申请日：2006-09-01

申请人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

发明人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

IPC分类号： H01L21/336 ,  H01L21/04 ,  H01L21/425

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

摘要翻译： 本发明提供一种晶体管器件的制造方法及其制造方法。 制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分 所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

公开(公告)号：US20080057654A1

公开(公告)日：2008-03-06

申请号：US11469512

申请日：2006-09-01

申请人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

发明人： Jihong Chen ,  Srinivasan Chakravarthi ,  Eddie H. Breashears ,  Amitabh Jain

IPC分类号： H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/6656 ,  H01L29/6659

摘要： The present invention provides a method for manufacturing a transistor device, and a method for manufacturing an integrated circuit including the same. The method for manufacturing the transistor device, among other elements, includes forming a gate structure over a substrate, implanting an atom selected from the group consisting of fluorine, silicon, or germanium into the substrate proximate the gate structure to cause at least a portion of the substrate to be in a sub-amorphous state, and implanting a dopant into the substrate having the implanted atom therein, thereby forming source/drain regions in the substrate, wherein the transistor device does not have a halo/pocket implant.

摘要翻译： 本发明提供一种晶体管器件的制造方法及其制造方法。 制造晶体管器件的方法以及其它元件包括在衬底上形成栅极结构，将选自氟，硅或锗的原子在栅极结构附近植入到衬底中，以使至少一部分 所述衬底处于亚非晶态，并且将掺杂剂注入到其中具有注入原子的衬底中，从而在衬底中形成源极/漏极区，其中所述晶体管器件不具有卤素/穴袋注入。

公开(公告)号：US08871025B2

公开(公告)日：2014-10-28

申请号：US12441583

申请日：2007-09-27

申请人： Avinash Gupta ,  Utpal K. Chakrabarti ,  Jihong Chen ,  Edward Semenas ,  Ping Wu

发明人： Avinash Gupta ,  Utpal K. Chakrabarti ,  Jihong Chen ,  Edward Semenas ,  Ping Wu

IPC分类号： C30B28/14 ,  C30B29/36 ,  C30B23/00

CPC分类号： C30B29/36 ,  C30B23/002 ,  C30B23/005

摘要： In a crystal growth method, a seed crystal 8 and a source material 4 are provided in spaced relation inside of a growth crucible 6. Starting conditions for the growth of a crystal 14 in the growth crucible 6 are then established therein. The starting conditions include: a suitable gas inside the growth crucible 6, a suitable pressure of the gas inside the growth crucible 6, and a suitable temperature in the growth crucible 6 that causes the source material 4 to sublimate and be transported via a temperature gradient in the growth crucible 6 to the seed crystal 8 where the sublimated source material precipitates. During growth of the crystal 14 inside the growth crucible 6, at least one of the following growth conditions are intermittently changed inside the growth crucible 6 a plurality of times: the gas in the growth crucible 6, the pressure of the gas in the growth crucible 6, and the temperature in the growth crucible 6.

摘要翻译： 在晶体生长方法中，种子晶体8和源材料4以生长坩埚6内的间隔关系设置。然后在其中建立用于在生长坩埚6中生长晶体14的起始条件。 起始条件包括：生长坩埚6内的合适气体，生长坩埚6内部的气体的适当压力，以及生长坩埚6中适当的温度，其使得源材料4升华并经由温度梯度 在生长坩埚6中，升华的源材料析出的晶种8。 在生长坩埚6内生长晶体14期间，生长坩埚6内的至少一个以下生长条件间歇性地变化：生长坩埚6中的气体，生长坩埚中的气体压力 6，以及生长坩埚6中的温度。

公开(公告)号：US20130192516A1

公开(公告)日：2013-08-01

申请号：US13360116

申请日：2012-01-27

申请人： Jihong Chen ,  Aditya Deshpande

发明人： Jihong Chen ,  Aditya Deshpande

IPC分类号： C30B19/08

CPC分类号： C30B11/002 ,  C30B11/14 ,  C30B29/06

摘要： A method of preparing a silicon melt in a crucible for use in the manufacture of cast silicon, wherein the crucible comprises an opening, an opposing bottom surface, and at least one sidewall joining the opening and the bottom surface. The method comprises charging a silicon spacer to the bottom surface of the crucible; arranging a monocrystalline silicon seed crystal on the silicon spacer such that no surface of the monocrystalline silicon material is in contact with the bottom surface of the crucible; charging polycrystalline silicon feedstock to the crucible; and applying heat through at least one of the opening and the at least one sidewall in order to form a partially melted charge of silicon in the crucible.

摘要翻译： 一种在用于制造铸硅的坩埚中制备硅熔体的方法，其中坩埚包括开口，相对的底表面和连接开口和底表面的至少一个侧壁。 该方法包括将硅隔离物装入坩埚的底表面; 在硅间隔物上布置单晶硅晶种，使得单晶硅材料的表面不与坩埚的底表面接触; 将多晶硅原料装入坩埚中; 并且通过所述开口和所述至少一个侧壁中的至少一个来施加热量，以便在所述坩埚中形成部分熔融的硅填充物。

公开(公告)号：US20050212041A1

公开(公告)日：2005-09-29

申请号：US11127941

申请日：2005-05-11

申请人： Zhiqiang Wu ,  Jihong Chen ,  Kaiping Liu

发明人： Zhiqiang Wu ,  Jihong Chen ,  Kaiping Liu

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/76

CPC分类号： H01L21/2652 ,  H01L21/823864 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66598 ,  H01L29/7833

摘要： A method of forming an associated transistor is presented whereby short channel effects and junction capacitances are mitigated and enhanced switching speeds are thereby facilitated. Compensation regions are formed within a substrate by implanting dopants relatively deeply over source and drain regions formed within the substrate. The compensation regions are spaced apart slightly less than are the source and drain regions. This spacing affects potential contours and reduces junction capacitances within the transistor. The different distances between the source and drain regions and the compensation regions are achieved by forming and selectively adjusting sidewall spacers adjacent to a gate structure of the transistor. These spacers serve as guides for the dopants implanted into the substrate to form the source and drain regions and the compensation regions.

摘要翻译： 提出了一种形成相关晶体管的方法，从而减轻了短沟道效应和结电容，从而促进了切换速度的提高。 通过在衬底内形成的源区和漏区相对深地注入掺杂剂，在衬底内形成补偿区。 补偿区域比源极和漏极区域稍微间隔开。 该间隔影响电位轮廓并降低晶体管内的结电容。 通过形成和选择性地调节与晶体管的栅极结构相邻的侧壁间隔来实现源极和漏极区域与补偿区域之间的不同距离。 这些间隔物用作植入衬底中的掺杂剂以形成源区和漏区以及补偿区的引导。

公开(公告)号：US07691714B2

公开(公告)日：2010-04-06

申请号：US11042415

申请日：2005-01-25

申请人： Antonio Luis Pacheco Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

发明人： Antonio Luis Pacheco Rotondaro ,  Kaiping Liu ,  Jihong Chen ,  Amitabh Jain

IPC分类号： H01L21/336 ,  H01L21/337

CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/823814 ,  H01L21/823871

摘要： The present invention provides a method for manufacturing a transistor device, a method for manufacturing an integrated circuit, and a transistor device. The method for manufacturing the transistor device, among other steps, includes forming a gate structure over a substrate and forming source/drain regions in the substrate proximate the gate structure, the source/drain regions having a boundary that forms an electrical junction with the substrate. The method further includes forming dislocation loops in the substrate, the dislocation loops not extending outside the boundary of the source/drain regions.

摘要翻译： 本发明提供了晶体管器件的制造方法，集成电路的制造方法以及晶体管器件。 制造晶体管器件的方法以及其他步骤包括在衬底上形成栅极结构，并在栅极结构附近形成衬底中的源极/漏极区域，源极/漏极区域具有与衬底形成电连接的边界 。 该方法还包括在衬底中形成位错环，位错环不延伸到源/漏区的边界之外。

公开(公告)号：US20100031877A1

公开(公告)日：2010-02-11

申请号：US12441583

申请日：2007-09-27

申请人： Avinash Gupta ,  Utpal K. Chakrabarti ,  Jihong Chen ,  Edward Semenas ,  Ping Wu

发明人： Avinash Gupta ,  Utpal K. Chakrabarti ,  Jihong Chen ,  Edward Semenas ,  Ping Wu

IPC分类号： C30B23/02

CPC分类号： C30B29/36 ,  C30B23/002 ,  C30B23/005

摘要： In a crystal growth method, a seed crystal 8 and a source material 4 are provided in spaced relation inside of a growth crucible 6. Starting conditions for the growth of a crystal 14 in the growth crucible 6 are then established therein. The starting conditions include: a suitable gas inside the growth crucible 6, a suitable pressure of the gas inside the growth crucible 6, and a suitable temperature in the growth crucible 6 that causes the source material 4 to sublimate and be transported via a temperature gradient in the growth crucible 6 to the seed crystal 8 where the sublimated source material precipitates. During growth of the crystal 14 inside the growth crucible 6, at least one of the following growth conditions are intermittently changed inside the growth crucible 6 a plurality of times: the gas in the growth crucible 6, the pressure of the gas in the growth crucible 6, and the temperature in the growth crucible 6.

摘要翻译： 在晶体生长方法中，种子晶体8和源材料4以生长坩埚6内的间隔关系设置。然后在其中建立用于在生长坩埚6中生长晶体14的起始条件。 起始条件包括：生长坩埚6内的合适气体，生长坩埚6内部的气体的适当压力，以及生长坩埚6中适当的温度，其使得源材料4升华并经由温度梯度 在生长坩埚6中，升华的源材料析出的晶种8。 在生长坩埚6内生长晶体14期间，生长坩埚6内的至少一个以下生长条件间歇性地变化：生长坩埚6中的气体，生长坩埚中的气体压力 6，以及生长坩埚6中的温度。

公开(公告)号：US20090181506A1

公开(公告)日：2009-07-16

申请号：US12407624

申请日：2009-03-19

申请人： Jihong Chen ,  Eddie Hearl Breashears ,  Xin Wang ,  John Howard Macpeak

发明人： Jihong Chen ,  Eddie Hearl Breashears ,  Xin Wang ,  John Howard Macpeak

IPC分类号： H01L21/8239 ,  H01L21/426

CPC分类号： H01L29/7881 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114

摘要： An embedded memory device and method of forming MOS transistors having reduced masking requirements and defects using a single drain sided halo implant in the NMOS FLASH or EEPROM memory regions is discussed. The memory device comprises a memory region and a logic region. Logic transistors within the logic region have halos implanted at an angle underlying the channel from both drain and source region sides. Asymmetric memory cell transistors within the memory region receive a selective halo implant only from the drain side of the channel and not from the source side to form a larger halo on the drain side and leave a higher dopant concentration more deeply into the source side. One method of asymmetrically forming memory cell transistors comprises masking over the memory region; halo implanting a first conductivity dopant in NMOS regions of the logic region in first and second implant directions; masking over the logic region; halo implanting the first conductivity dopant in NMOS regions of the memory region in the second implant direction only, thereby reducing the number of masks required; masking over the memory region; halo implanting a second conductivity dopant in PMOS regions of the logic region in the first and second implant directions.

摘要翻译： 讨论了在NMOS闪存或EEPROM存储器区域中使用单个漏极侧卤素注入形成具有减小的掩模要求和缺陷的MOS晶体管的嵌入式存储器件和方法。 存储器件包括存储器区域和逻辑区域。 逻辑区域内的逻辑晶体管具有从沟道和源极区两侧的通道下方的角度注入的光晕。 存储器区域内的不对称存储单元晶体管仅从沟道的漏极侧接收选择性晕圈注入而不从源极接收，以在漏极侧形成较大的卤素，并且在源极侧更高的掺杂浓度。 一种不对称形成存储单元晶体管的方法包括：对存储区进行掩蔽; 在第一和第二植入方向上在所述逻辑区域的NMOS区域中注入第一电导率掺杂剂; 屏蔽逻辑区域; 在第二注入方向仅在存储区域的NMOS区域中注入第一电导率掺杂剂，从而减少所需的掩模数量; 掩蔽内存区域; 在所述第一和第二植入方向上在所述逻辑区域的PMOS区域中注入第二电导率掺杂剂。