公开(公告)号：US07202164B2

公开(公告)日：2007-04-10

申请号：US10992894

申请日：2004-11-19

申请人： Jinping Liu ,  Hwa Weng Koh ,  Dong Kyun Sohn ,  Liang Choo Hsia

发明人： Jinping Liu ,  Hwa Weng Koh ,  Dong Kyun Sohn ,  Liang Choo Hsia

IPC分类号： H01L21/8238

CPC分类号： H01L21/0214 ,  H01L21/02238 ,  H01L21/02332 ,  H01L21/265 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/3144 ,  H01L29/518

摘要： A method of forming a gate dielectric layer is disclosed. The method comprises the following steps. A substrate is provided having silicon regions containing surfaces upon which gate dielectrics are to be disposed. An oxide is formed over the surfaces. A silicon layer is formed over the oxide layer. A nitridation process is performed. An optional high temperature annealing step may be performed.

摘要翻译： 公开了一种形成栅介质层的方法。 该方法包括以下步骤。 提供了具有硅区域的衬底，所述硅区域包含要在其上设置栅极电介质的表面。 在表面上形成氧化物。 在氧化物层上形成硅层。 进行氮化处理。 可以进行可选的高温退火步骤。

公开(公告)号：US07338886B2

公开(公告)日：2008-03-04

申请号：US11107712

申请日：2005-04-15

申请人： Jinping Liu ,  Dong Kyun Sohn ,  Liang Choo Hsia

发明人： Jinping Liu ,  Dong Kyun Sohn ,  Liang Choo Hsia

IPC分类号： H01L21/20

CPC分类号： H01L29/1054 ,  H01L21/02381 ,  H01L21/02395 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/76262 ,  H01L29/78 ,  Y10S438/933

摘要： A method of fabricating a semiconductor substrate includes forming a buffer layer on the substrate. A Ge containing layer, such as a SiGe is formed over the buffer layer. The buffer layer includes defects at the interface of the substrate and buffer layer. The substrate is oxidized to transform the buffer layer to a buried oxide layer.

摘要翻译： 制造半导体衬底的方法包括在衬底上形成缓冲层。 在缓冲层之上形成Ge含Ge层，例如SiGe。 缓冲层包括在衬底和缓冲层的界面处的缺陷。 将衬底氧化以将缓冲层转变成掩埋氧化物层。

公开(公告)号：US20090315115A1

公开(公告)日：2009-12-24

申请号：US12214854

申请日：2008-06-23

申请人： Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

发明人： Beichao Zhang ,  Johnny Widodo ,  Juan Boon Tan ,  Yong Kong Siew ,  Fan Zhang ,  Haifeng Sheng ,  Wenhe Lin ,  Young Way Teh ,  Jinping Liu ,  Vincent Ho ,  Liang Choo Hsia

IPC分类号： H01L21/8234 ,  H01L27/088

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L29/7846

摘要： A method (and semiconductor device) of fabricating a semiconductor device provides a shallow trench isolation (STI) structure or region by implanting ions in the STI region. After implantation, the region (of substrate material and ions of a different element) is thermally annealed producing a dielectric material operable for isolating two adjacent field-effect transistors (FET). This eliminates the conventional steps of removing substrate material to form the trench and refilling the trench with dielectric material. Implantation of nitrogen ions into an STI region adjacent a p-type FET applies a compressive stress to the transistor channel region to enhance transistor performance. Implantation of oxygen ions into an STI region adjacent an n-type FET applies a tensile stress to the transistor channel region to enhance transistor performance.

摘要翻译： 制造半导体器件的方法（和半导体器件）通过在STI区域中注入离子来提供浅沟槽隔离（STI）结构或区域。 在植入之后，区域（衬底材料和不同元素的离子）进行热退火，产生用于隔离两个相邻的场效应晶体管（FET）的电介质材料。 这消除了去除衬底材料以形成沟槽并用电介质材料重新填充沟槽的常规步骤。 将氮离子注入到邻近p型FET的STI区域中，对晶体管沟道区域施加压缩应力以增强晶体管性能。 将氧离子注入到与n型FET相邻的STI区域中，对晶体管沟道区域施加拉伸应力以增强晶体管性能。

公开(公告)号：US08716076B2

公开(公告)日：2014-05-06

申请号：US13190805

申请日：2011-07-26

申请人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/338

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US08012839B2

公开(公告)日：2011-09-06

申请号：US12040562

申请日：2008-02-29

申请人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/336

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US20090218597A1

公开(公告)日：2009-09-03

申请号：US12040562

申请日：2008-02-29

申请人： Jinping Liu ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex KH See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US20090053864A1

公开(公告)日：2009-02-26

申请号：US11844074

申请日：2007-08-23

申请人： Jinping Liu ,  Alex K.H. See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K.H. See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02546 ,  H01L21/02609 ,  H01L29/045

摘要： A method for fabricating a semiconductor structure having heterogeneous crystalline orientations by forming a region including a semiconductor material having a specified crystalline orientation using an epitaxial buffer overlying a semiconductor substrate. The buffer provides a transfer body such that the semiconductor material has a crystalline orientation that differs from the crystalline orientation of a semiconductor region underlying the buffer. The method also includes fabricating a semiconductor structure having a p-type device region and an n-type device region, where a supporting semiconductor substrate is either n-type or p-type and where the semiconductor material is separated from the substrate by a buffer and has a crystalline orientation that differs from the crystalline orientation of the substrate.

摘要翻译： 一种通过使用覆盖在半导体衬底上的外延缓冲层形成包含具有指定结晶取向的半导体材料的区域来制造具有异质结晶取向的半导体结构的方法。 缓冲器提供转移体，使得半导体材料具有不同于缓冲器下面的半导体区域的晶体取向的结晶取向。 该方法还包括制造具有p型器件区域和n型器件区域的半导体结构，其中支持半导体衬底是n型或p型，并且半导体材料通过缓冲器与衬底分离 并且具有不同于衬底的晶体取向的结晶取向。

公开(公告)号：US20090088002A1

公开(公告)日：2009-04-02

申请号：US11862865

申请日：2007-09-27

申请人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. See ,  Meisheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Ben Ong ,  Zhengquan Zhang ,  Jae Gon Lee ,  Lydia Wong ,  Bin Yang ,  K. H. See ,  Meisheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/31

CPC分类号： H01L21/3143 ,  H01L21/0214 ,  H01L21/02332 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

摘要： A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides opposite the interface region. Nitrogen is introduced into the silicon oxide layer by applying a nitrogen plasma. After applying nitrogen plasma, the silicon oxide layer is annealed. The processes of introducing nitrogen into the silicon oxide layer and annealing the silicon oxide layer are repeated to create a bi-modal nitrogen concentration profile in the silicon oxide layer. In the silicon oxide layer, the peak nitrogen concentrations are situated away from the interface region and at least one of the peak nitrogen concentrations is situated in proximity to the surface region. A method for fabricating a semiconductor device is incorporating the nitrogen-containing silicon oxide layers also disclosed.

摘要翻译： 一种含氮介电层的制造方法和包括在基板上形成氧化硅层的电介质层的半导体器件，使得界面区域与基板相邻，表面区域与界面区域相对。 通过施加氮等离子体将氮引入到氧化硅层中。 在施加氮等离子体之后，将氧化硅层退火。 重复将氧气引入氧化硅层并退火氧化硅层的过程，以在氧化硅层中产生双峰氮浓度分布。 在氧化硅层中，峰值氮浓度远离界面区域，并且峰值氮浓度中的至少一个位于表面区域附近。 还公开了一种制造半导体器件的方法，其中还包括含氮氧化硅层。

公开(公告)号：US08546873B2

公开(公告)日：2013-10-01

申请号：US13241215

申请日：2011-09-23

申请人： Jinping Liu ,  Hai Cong ,  Binbin Zhou ,  Alex Kh See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Hai Cong ,  Binbin Zhou ,  Alex Kh See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L29/66

CPC分类号： H01L21/823468 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.

摘要翻译： 一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物 在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。

公开(公告)号：US08058123B2

公开(公告)日：2011-11-15

申请号：US11946843

申请日：2007-11-29

申请人： Jinping Liu ,  Hai Cong ,  Binbin Zhou ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Hai Cong ,  Binbin Zhou ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/8238

CPC分类号： H01L21/823468 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/7848

摘要： A method of forming an integrated circuit structure comprising the steps of forming a first and second device region on a surface of a wafer, forming a spacer of a first width on a sidewall of a first gate stack in the first device region, forming a spacer of a second width on a sidewall of a second gate stack in the second device region, with the first width being different from the second width.

摘要翻译： 一种形成集成电路结构的方法，包括以下步骤：在晶片的表面上形成第一和第二器件区域，在第一器件区域中的第一栅极堆叠的侧壁上形成第一宽度的间隔物，形成间隔物 在第二装置区域中的第二栅极堆叠的侧壁上具有第二宽度，第一宽度不同于第二宽度。