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1.发明授权Phase change memory element with a peripheral connection to a thin film electrode 有权具有与薄膜电极的周边连接的相变存储元件公开(公告)号：US07923712B2
公开(公告)日：2011-04-12
申请号：US12492618
申请日：2009-06-26
申请人： John Christopher Arnold , Lawrence Alfred Clevenger , Timothy Joseph Dalton , Michael Christopher Gaidis , Louis L. Hsu , Carl John Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： John Christopher Arnold , Lawrence Alfred Clevenger , Timothy Joseph Dalton , Michael Christopher Gaidis , Louis L. Hsu , Carl John Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L29/02
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.
摘要翻译： PCM单元结构包括第一电极，相变元件和第二电极，其中相变元件插入在第一电极和第二电极之间，并且仅第一电极的周边边缘与相变元件接触， 减少相变元件与第一电极之间的接触面积，从而增加通过相变元件的电流密度，并有效地在较低的电流电平和降低的编程功率下引起相变。
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2.发明申请Method for delineation of phase change memory cell via film resistivity modification 有权通过膜电阻率修饰来描绘相变记忆单元的方法公开(公告)号：US20100001253A1
公开(公告)日：2010-01-07
申请号：US12492618
申请日：2009-06-26
申请人： John Christopher Arnold , Lawrence Alfred Clevenger , Timothy Joseph Dalton , Michael Christopher Gaidis , Louis L. Hsu , Carl John Radens , Keith Kwong Hon Wong , Chih-Chao Yang
发明人： John Christopher Arnold , Lawrence Alfred Clevenger , Timothy Joseph Dalton , Michael Christopher Gaidis , Louis L. Hsu , Carl John Radens , Keith Kwong Hon Wong , Chih-Chao Yang
IPC分类号： H01L45/00
CPC分类号： H01L45/1675 , H01L45/06 , H01L45/122 , H01L45/1233 , H01L45/126 , H01L45/144
摘要： A PCM cell structure comprises a first electrode, a phase change element, and a second electrode, wherein the phase change element is inserted in between the first electrode and the second electrode and only the peripheral edge of the first electrode contacts the phase change element thereby reducing the contact area between the phase change element and the first electrode and thereby increasing the current density through the phase change element and effectively inducing the phase change at lower levels of current and reduced programming power.
摘要翻译： PCM单元结构包括第一电极，相变元件和第二电极，其中相变元件插入在第一电极和第二电极之间，并且仅第一电极的周边边缘与相变元件接触， 减少相变元件与第一电极之间的接触面积，从而增加通过相变元件的电流密度，并有效地在较低的电流电平和降低的编程功率下引起相变。
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公开(公告)号：US08298943B1
公开(公告)日：2012-10-30
申请号：US13118034
申请日：2011-05-27
IPC分类号： H01L21/311 , H01L21/44
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76811 , H01L21/76816 , H01L21/76897
摘要： A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. The first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.
摘要翻译： 用于在电介质中图案化自对准通孔的方法。 该方法包括通过硬掩模部分地形成第一沟槽，其中沟槽对应于电介质中期望的布线路径。 沟槽应该在亚光刻尺上形成。 形成与第一沟槽相交的第二沟槽，也是亚光刻标尺。 交叉点形成延伸穿过硬掩模的深度的图案，并且对应于电介质中的通孔。 通孔通过硬掩模蚀刻到电介质中。 第一沟槽延伸穿过硬掩模，并且暴露区域被蚀刻以形成与通孔相交的布线路径。 导电材料沉积以形成亚光刻通孔和布线。 该方法可以用于形成亚光刻比例的多个通孔和亚光刻间距。
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公开(公告)号：US08012811B2
公开(公告)日：2011-09-06
申请号：US11968778
申请日：2008-01-03
IPC分类号： H01L21/82
CPC分类号： H01L21/0337 , Y10T428/24612
摘要： A feature is formed in an integrated circuit by providing one or more layers to be patterned, providing a first layer overlying the one or more layers to be patterned, and providing a second layer overlying the first layer. The second layer is patterned to form a raised feature with one or more sidewalls. Subsequently, the first layer is processed such that components of the first layer deposit on the one or more sidewalls of the raised feature to form a mask. The mask is used to pattern the one or more layers to be patterned.
摘要翻译： 通过提供一个或多个要图案化的层来形成集成电路中的特征，提供覆盖待图案化的一个或多个层的第一层，以及提供覆盖第一层的第二层。 图案化第二层以形成具有一个或多个侧壁的凸起特征。 随后，处理第一层，使得第一层的组分沉积在凸起特征的一个或多个侧壁上以形成掩模。 该掩模用于对要图案化的一层或多层进行图案化。
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5.发明申请公开(公告)号：US20090179186A1
公开(公告)日：2009-07-16
申请号：US12407068
申请日：2009-03-19
IPC分类号： H01L47/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/165 , H01L45/1666 , Y10S977/734
摘要： A Phase Change Memory (PCM) cell structure comprises both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM layer is protected from damage by the conductive encapsulating layer. Electrical isolation between adjacent PCM cells is provided by high electrical resistance regions which were formed by modifying the conductivity of both the PCM layer and the conductive encapsulating upper electrode layer subsequent to deposition thereof.
摘要翻译： 相变存储器（PCM）单元结构包括由PCM层构成的下电极和导电封装上电极层。 保护PCM层免受导电封装层的损伤。 在相邻PCM单元之间的电隔离由高电阻区域提供，高电阻区域是通过在其沉积之后修改PCM层和导电封装上电极层的导电性而形成的。
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公开(公告)号：US08518824B2
公开(公告)日：2013-08-27
申请号：US13558441
申请日：2012-07-26
IPC分类号： H01L21/311 , H01L21/44 , H01L21/00
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76811 , H01L21/76816 , H01L21/76897
摘要： A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.
摘要翻译： 用于在电介质中图案化自对准通孔的方法。 该方法包括通过硬掩模部分地形成第一沟槽，其中沟槽对应于电介质中期望的布线路径。 沟槽应该在亚光刻尺上形成。 然后，形成与第一沟槽相交的第二沟槽，也是亚光刻标尺。 交叉点形成延伸穿过硬掩模的深度的图案，并且对应于电介质中的通孔。 通孔通过硬掩模蚀刻到电介质中。 然后将第一沟槽延伸穿过硬掩模，并且暴露的区域被蚀刻以形成与通孔相交的布线路径。 导电材料沉积以形成亚光刻通孔和布线。 该方法可以用于形成亚光刻比例的多个通孔和亚光刻间距。
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7.发明授权Method for delineation of phase change memory (PCM) cells separated by PCM and upper electrode regions modified to have high film resistivity 有权用PCM划分的相变存储器（PCM）单元的描述方法和修改为具有高膜电阻率的上电极区域公开(公告)号：US07550313B2
公开(公告)日：2009-06-23
申请号：US11781239
申请日：2007-07-21
IPC分类号： H01L21/00
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/165 , H01L45/1666 , Y10S977/734
摘要： A method for forming a Phase Change Material (PCM) cell structure comprises forming both a lower electrode composed of a PCM layer and a conductive encapsulating upper electrode layer. The PCM is protected from damage by a conductive encapsulating layer. Electrical isolation between adjacent cells is provided by modifying the conductivity of both the PCM layer and the conductive encapsulating upper electrode layer subsequent to deposition thereof, thereby forming high electrical resistance regions between the cells.
摘要翻译： 形成相变材料（PCM）单元结构的方法包括形成由PCM层构成的下电极和导电封装上电极层。 保护PCM免受导电封装层的损坏。 通过在其沉积之后修改PCM层和导电封装上电极层的电导率来提供相邻电池之间的电隔离，由此在电池之间形成高电阻区域。
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8.发明申请Method for Delineation of Phase Change Memory Cell Via Film Resistivity Modification 有权通过薄膜电阻率改性来描绘相变记忆单元的方法公开(公告)号：US20090020739A1
公开(公告)日：2009-01-22
申请号：US11781239
申请日：2007-07-21
CPC分类号： H01L45/144 , G11C13/0004 , H01L27/2472 , H01L45/06 , H01L45/1233 , H01L45/165 , H01L45/1666 , Y10S977/734
摘要： A PCM cell structure comprises a lower electrode composed of a Phase Change Memory (PCM) layer and a conductive encapsulating upper electrode layer. The PCM is protected from damage by a conductive encapsulating layer. Electrical isolation between adjacent cells is provided by modifying the conductivity of the PCM layer and the conductive encapsulating upper electrode layer subsequent to deposition.
摘要翻译： PCM单元结构包括由相变存储器（PCM）层和导电封装上电极层组成的下电极。 保护PCM免受导电封装层的损坏。 通过在沉积之后修改PCM层和导电封装上电极层的电导率来提供相邻电池之间的电隔离。
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公开(公告)号：US20120302057A1
公开(公告)日：2012-11-29
申请号：US13558441
申请日：2012-07-26
IPC分类号： H01L21/768
CPC分类号： H01L21/31144 , H01L21/0337 , H01L21/0338 , H01L21/76811 , H01L21/76816 , H01L21/76897
摘要： A method for patterning self-aligned vias in a dielectric. The method includes forming a first trench partially through a hard mask, where the trench corresponds to a desired wiring path in the dielectric. The trench should be formed on a sub-lithographic scale. Then, form a second trench, also of a sub-lithographic scale, that intersects the first trench. The intersection forms a pattern extending through the depth of the hard mask, and corresponds to a via hole in the dielectric. The via hole is etched into the dielectric through the hard mask. Then the first trench is extended through the hard mask and the exposed area is etched to form the wiring path, which intersects the via hole. Conductive material is deposited to form a sub-lithographic via and wiring. This method may be used to form multiple vias of sub-lithographic proportions and with a sub-lithographic pitch.
摘要翻译： 用于在电介质中图案化自对准通孔的方法。 该方法包括通过硬掩模部分地形成第一沟槽，其中沟槽对应于电介质中期望的布线路径。 沟槽应该在亚光刻尺上形成。 然后，形成与第一沟槽相交的第二沟槽，也是亚光刻标尺。 交叉点形成延伸穿过硬掩模的深度的图案，并且对应于电介质中的通孔。 通孔通过硬掩模蚀刻到电介质中。 然后将第一沟槽延伸穿过硬掩模，并且暴露的区域被蚀刻以形成与通孔相交的布线路径。 导电材料沉积以形成亚光刻通孔和布线。 该方法可以用于形成亚光刻比例的多个通孔和亚光刻间距。
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公开(公告)号：US08168542B2
公开(公告)日：2012-05-01
申请号：US11968771
申请日：2008-01-03
IPC分类号： H01L21/311
CPC分类号： C01B21/0602 , B82Y30/00 , C01P2004/13 , C01P2004/133 , Y10T428/13
摘要： A tubular object is fabricated by a method comprising the steps of providing a first layer, forming a second layer on the first layer, and then patterning the second layer to form a raised feature with one or more sidewalls. Subsequently, the first layer is processed such that components of the first layer deposit on the one or more sidewalls of the raised feature.
摘要翻译： 通过包括以下步骤的方法制造管状物体，所述方法包括提供第一层，在第一层上形成第二层，然后图案化第二层以形成具有一个或多个侧壁的凸起特征。 随后，处理第一层，使得第一层的组分沉积在凸起特征的一个或多个侧壁上。
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