公开(公告)号：US06965503B2

公开(公告)日：2005-11-15

申请号：US10605441

申请日：2003-09-30

申请人： John Connor ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Alan L. Roberts

发明人： John Connor ,  Robert J. Gauthier, Jr. ,  Christopher S. Putnam ,  Alan L. Roberts

IPC分类号： H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0285

摘要： An ESD protection circuit including the following: one or more inverters (I1, I2, I3), each of the one or more inverters having an input and an output; an RC network (11) having an output node (RCT), output node (RCT) connected with the input of at least one of said one or more inverters; a clamping device (N3) joined with the output of at least one of one or more inverters (I1, I2, I3); and a feedback device (NKP) in communication with clamping device (N3) and output node (RCT) of RC network (11). An RC network may include one or more resistors, and one or more decoupling capacitors. In one embodiment, feedback device (NKP) is an NFET and each of one or more inverters (I1, I2, I3) includes a PFET and NFET pair (P0/N0, P1/N1, P2/N2).

摘要翻译： 一种ESD保护电路，包括：一个或多个反相器（I 1，I 2，I 3），一个或多个反相器中的每一个具有输入和输出; 具有输出节点（RCT）的RC网络（11），与所述一个或多个逆变器中的至少一个的输入端连接的输出节点（RCT） 与一个或多个逆变器（I 1，I 2，I 3）中的至少一个的输出端连接的夹持装置（N 3）; 以及与RC网络（11）的钳位装置（N 3）和输出节点（RCT）通信的反馈装置（NKP）。 RC网络可以包括一个或多个电阻器和一个或多个去耦电容器。 在一个实施例中，反馈装置（NKP）是NFET，并且一个或多个反相器（I 1，I 2，I 3）中的每一个包括PFET和NFET对（P 0 / N 0，P 1 / N 1，P 2 / N 2）。

公开(公告)号：US5563833A

公开(公告)日：1996-10-08

申请号：US398465

申请日：1995-03-03

申请人： Robert D. Adams ,  John Connor ,  James J. Covino ,  Roy C. Flaker ,  Garrett S. Koch ,  Alan L. Roberts ,  Jose R. Sousa ,  Luigi Ternullo, Jr.

发明人： Robert D. Adams ,  John Connor ,  James J. Covino ,  Roy C. Flaker ,  Garrett S. Koch ,  Alan L. Roberts ,  Jose R. Sousa ,  Luigi Ternullo, Jr.

IPC分类号： G06F12/16 ,  G06F12/08 ,  G11C8/10 ,  G11C15/00 ,  G11C15/04 ,  G11C29/00 ,  G11C29/02 ,  G11C29/10 ,  G11C29/12 ,  G11C29/56 ,  G11C7/00

CPC分类号： G11C29/12 ,  G06F12/0893 ,  G11C15/00 ,  G11C8/10 ,  G11C29/10

摘要： An associated memory structure having a plurality of memories amenable for testing and a method of testing the memories is provided. First and second memories are formed, wherein data in the first memory provides a basis for at least a portion of the input to the second memory during functional operation of two memories. Preferably, an output latch for receiving the output test data from the first memory is provided. Means are provided for loading the first memory with data which is utilized as a basis for providing at least a portion of the input to the second memory. An access path from the output port of the first memory to the input port of the second memory allows use of the data in the first memory to generate at least a portion of the input to the second memory. The first memory is first tested independently of the second memory. Thereafter, the first memory is loaded with preconditioned data that is used as a basis for inputs to the second memory during testing of the second memory. The second memory is then tested by generating inputs to the first memory during testing of the second memory. Thus, outputs of the first memory constitute at least a portion of test data inputted to the second memory. A latch is provided to capture the output of the test data from the second memory.

摘要翻译： 提供了具有适于测试的多个存储器的关联存储器结构和测试存储器的方法。 形成第一和第二存储器，其中在两个存储器的功能操作期间，第一存储器中的数据为至少一部分输入提供基础。 优选地，提供用于从第一存储器接收输出测试数据的输出锁存器。 提供了用于将数据加载到第一存储器的装置，该数据被用作将至少一部分输入提供给第二存储器的基础。 从第一存储器的输出端口到第二存储器的输入端口的访问路径允许使用第一存储器中的数据来生成至第二存储器的输入的至少一部分。 第一个内存首先被独立于第二个内存进行测试。 此后，第一存储器加载预测数据，该预处理数据在第二存储器测试期间用作输入到第二存储器的基础。 然后在测试第二个存储器期间通过产生第一个存储器的输入来测试第二个存储器。 因此，第一存储器的输出构成输入到第二存储器的测试数据的至少一部分。 提供锁存器以捕获来自第二存储器的测试数据的输出。

公开(公告)号：US07291399B2

公开(公告)日：2007-11-06

申请号：US10821760

申请日：2004-04-09

申请人： Samuel Kaplan ,  Santokh Badesha ,  Mark Amico ,  Alexander Klymachyov ,  Johan Marien van der Werf ,  Peter MHM Peeters ,  John Connor ,  Peter Karran ,  Louis D. Fratangelo ,  Mark John Lillie

发明人： Samuel Kaplan ,  Santokh Badesha ,  Mark Amico ,  Alexander Klymachyov ,  Johan Marien van der Werf ,  Peter MHM Peeters ,  John Connor ,  Peter Karran ,  Louis D. Fratangelo ,  Mark John Lillie

IPC分类号： G03G13/20

CPC分类号： G03G15/2025 ,  G03G15/2057 ,  Y10T428/3154 ,  Y10T428/31663

摘要： Disclosed is a fuser member comprising a substrate, a layer thereover comprising a polymer or an elastomer, and, on the layer, a coating including mercapto- and amino-functionalities comprising from about 0.05 mole percent to about 1.00 mole percent mercapto groups and from about 0.0001 mole percent to about 0.06 mole percent amino groups, wherein the ratio of mercapto to amino mole percent values is at least 2. The layer preferably is a fluoropolymer or fluoroelastomer filled with a metal oxide (CuO, Al2O3, etc.).

摘要翻译： 公开了一种定影器构件，其包括基底，其上包含聚合物或弹性体的层，并且在该层上，包含巯基和氨基官能团的涂层，其包含约0.05摩尔％至约1.00摩尔％的巯基和约 0.0001摩尔％至约0.06摩尔％的氨基，其中巯基与氨基摩尔百分比的比值至少为2.该层优选为填充有金属氧化物（CuO，Al 2 O 3）的含氟聚合物或含氟弹性体 > O 3等）。

公开(公告)号：US06278339B1

公开(公告)日：2001-08-21

申请号：US09735679

申请日：2000-12-13

申请人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

发明人： Wagdi W. Abadeer ,  John Connor ,  Patrick R. Hansen

IPC分类号： H03H738

摘要： An impedance matching system and a network for impedance matching at a driver circuit output for high frequency input-output devices. The impedance matching network comprises an adjustable-length transmission line having a length adjusted in proportion to the magnitude of transients on the driver circuit output and an input impedance, which is purely reactive, and is a function of its length. The purpose of the adjustable-length transmission line is to reduce transient voltages by providing a matching impedance for the reactive component of the impedance of the receiver circuit to the driver circuit. In the preferred embodiment, the impedance matching network comprises two parallel conductive lines formed on the system card, shorted by a movable stub, and connected in parallel to the driver circuit. Optionally, the impedance matching network further comprises a control circuit which detects overshoots and undershoots on the driver circuit output and provides a control current proportional to the magnitude of overshoots and undershoots to an electromagnetic adjustment mechanism which provides a linear adjustment to the moveable stub proportional to the control current.

公开(公告)号：US5815354A

公开(公告)日：1998-09-29

申请号：US821497

申请日：1997-03-21

申请人： George Maria Braceras ,  John Connor ,  Donald Albert Evans

发明人： George Maria Braceras ,  John Connor ,  Donald Albert Evans

IPC分类号： H02H9/04 ,  H02H9/00

CPC分类号： H02H9/046

摘要： An off-chip receiver circuit for interfacing an integrated circuit of a 2.5 Volt CMOS technology to a 3.3 Volt LVTTL bus. The off-chip receiver includes protection circuitry for preventing overstressing of the gate oxide caused by undershoot/overshoot peaks of -1 volt to 6 volts on the input.

摘要翻译： 用于将2.5伏CMOS技术的集成电路与3.3伏的LVTTL总线接口的片外接收器电路。 片外接收器包括用于防止由输入端上的-1伏至6伏特的下冲/过冲峰值引起的栅极氧化物的过应力的保护电路。

公开(公告)号：US4740028A

公开(公告)日：1988-04-26

申请号：US937062

申请日：1986-11-05

申请人： John Connor

发明人： John Connor

IPC分类号： B60J3/02

CPC分类号： B60J3/0282

摘要： Sunvisors provided with vanity mirrors usually have the mirror, with or without illumination, fixed to the upper surface of the visor when in the stowed position, and to avoid undesirable reflections a cover is sometimes provided. Also, various switches are provided to control energization of the lighting means when present. The invention simplifies this kind of visor by arranging that the mirror is carried by a hinge (7b) near the lower margins of the visor to open out therefrom downwardly from a stowed position facing into a recess (11) in the upper surface of the visor. The lower edge of the visor may be relieved as at (12) to maximize the hingeing angle of the mirror so as to achieve compactness while satisfying visor safety requirements. The wire frame (7) of the visor may be joggled inwards at (7a) and (8a) to provide hinge pins and electrical connections (7b) and (8b) for the visor.

摘要翻译： PCT No.PCT / GB86 / 00111 Sec。 371日期：1986年11月5日 102（e）日期1986年11月5日PCT Filted Mar 3，1986 PCT Pub。 出版物WO86 / 05146 日期为1986年9月12日。设有梳妆镜的管家通常具有镜子，有或没有照明，在收纳位置时固定在遮阳板的上表面，并且为了避免不必要的反射，有时会提供盖子。 此外，提供各种开关以控制当存在时照明装置的通电。 本发明通过将镜子布置在靠近遮阳板的下边缘处的铰链（7b）来简化这种遮阳板，以便从面向在遮阳板的上表面中的凹槽（11）的收起位置向下打开 。 如（12）所示，遮阳板的下边缘可以减轻以最大化反射镜的铰接角度，以便在满足遮阳板安全要求的同时实现紧凑性。 在（7a）和（8a）处，遮阳板的线框架（7）可向内倾斜，以提供用于遮阳板的铰链销和电连接（7b）和（8b）。

公开(公告)号：US07496398B2

公开(公告)日：2009-02-24

申请号：US10260719

申请日：2002-09-27

申请人： Morgan W. Nields ,  John Connor ,  Curtis Daly

发明人： Morgan W. Nields ,  John Connor ,  Curtis Daly

IPC分类号： A61B6/02

CPC分类号： A61B6/502 ,  A61B6/0435 ,  A61B6/4417 ,  A61B6/463 ,  A61B6/465 ,  A61B6/469 ,  A61B6/5247 ,  A61B8/0825 ,  A61B8/406 ,  A61B8/4416 ,  A61B8/463 ,  A61B8/464 ,  A61B8/465 ,  A61B8/467 ,  A61B8/469 ,  A61B8/5238 ,  Y10S128/915 ,  Y10S128/916

摘要： The present invention provides for x-ray imaging and ultrasound imaging of a body region of interest in a spatially correlatable manner. The resultant x-ray and ultrasound images may be combinatively employed to provide three-dimensional information regarding a location of interest within the body, and is particularly apt for use in the analysis/biopsy of potential lesions and suspicious masses in a female breast. The invention provides for direct body contact by an ultrasound imaging head, as well as targeted ultrasound imaging of a selected portion of the region from which x-ray images are obtained. A user interface system facilitates various procedures including ultrasound guided needle biopsy procedures.

摘要翻译： 本发明以空间可相关的方式提供感兴趣的身体区域的X射线成像和超声成像。 可以组合使用所得的X射线和超声图像以提供关于身体内的感兴趣位置的三维信息，并且特别适合用于女性乳房中潜在损伤和可疑肿块的分析/活检。 本发明提供了通过超声成像头的直接身体接触以及从其获得X射线图像的区域的选定部分的目标超声成像。 用户界面系统促进包括超声引导针活检程序在内的各种程序。

公开(公告)号：US06501293B2

公开(公告)日：2002-12-31

申请号：US09439787

申请日：1999-11-12

申请人： George M. Braceras ,  John Connor ,  Patrick R. Hansen

发明人： George M. Braceras ,  John Connor ,  Patrick R. Hansen

IPC分类号： H03K19003

CPC分类号： H04L25/0298

摘要： A method and apparatus for providing programmable active termination of transmission lines with substantially reduced DC power consumption.

摘要翻译： 一种用于以显着降低的DC功率消耗提供传输线的可编程有源终端的方法和装置。

公开(公告)号：US06459925B1

公开(公告)日：2002-10-01

申请号：US09449267

申请日：1999-11-24

申请人： Morgan W. Nields ,  John Connor ,  Curtis Daly

发明人： Morgan W. Nields ,  John Connor ,  Curtis Daly

IPC分类号： A61B505

CPC分类号： A61B6/502 ,  A61B6/0435 ,  A61B6/4417 ,  A61B6/463 ,  A61B6/465 ,  A61B6/469 ,  A61B6/5247 ,  A61B8/0825 ,  A61B8/406 ,  A61B8/4416 ,  A61B8/463 ,  A61B8/464 ,  A61B8/465 ,  A61B8/467 ,  A61B8/469 ,  A61B8/5238 ,  Y10S128/915 ,  Y10S128/916

摘要： The present invention provides for x-ray imaging and ultrasound imaging of a body region of interest in a spatially correlatable manner. The resultant x-ray and ultrasound images may be combinatively employed to provide three-dimensional information regarding a location of interest within the body, and is particularly apt for use in the analysis/biopsy of potential lesions and suspicious masses in a female breast. The invention provides for direct body contact by an ultrasound imaging head, as well as targeted ultrasound imaging of a selected portion of the region from which x-ray images are obtained. A user interface system facilitates various procedures including ultrasound guided needle biopsy procedures.

摘要翻译： 本发明以空间可相关的方式提供感兴趣的身体区域的X射线成像和超声成像。 可以组合使用所得的X射线和超声图像以提供关于身体内的感兴趣位置的三维信息，并且特别适合用于女性乳房中潜在损伤和可疑肿块的分析/活检。 本发明提供了通过超声成像头的直接身体接触以及从其获得X射线图像的区域的选定部分的目标超声成像。 用户界面系统促进包括超声引导针活检程序在内的各种程序。

公开(公告)号：US5771242A

公开(公告)日：1998-06-23

申请号：US721601

申请日：1996-09-25

申请人： Robert Dean Adams ,  John Connor ,  Garrett Stephen Koch ,  Luigi Ternullo, Jr.

发明人： Robert Dean Adams ,  John Connor ,  Garrett Stephen Koch ,  Luigi Ternullo, Jr.

IPC分类号： G11C29/12 ,  G11C29/10 ,  G11C29/36 ,  G01R31/28

CPC分类号： G11C29/36

摘要： An ABIST circuit for testing a memory array has a blanket write subcycle (WC), an RC.sub.3 subcycle, and an RC.sub.4 subcycle. The ABIST circuit includes a programmable pattern generator that provides eight programmable data bits, eight programmable read/write bits, and two programmable address frequency bits to determine the specific test patterns applied to the memory array. The address frequency bits determine how many memory cycles will be performed on each cell of the memory array. In X1 mode, only one memory cycle is performed on each cell during any given subcycle. In X2 mode, two memory cycles are performed on each cell, allowing a cell to be written, then subsequently read in the same subcycle, In X4 mode, four memory cycles are performed on each cell, and in Xg mode, all eight bits of read/write and data are used on each cell, resulting in eight memory cycles for each cell within the memory array.

摘要翻译： 用于测试存储器阵列的ABIST电路具有毯子写入子周期（WC），RC3子周期和RC4子周期。 ABIST电路包括一个可编程模式发生器，提供八个可编程数据位，八个可编程读/写位和两个可编程地址频率位，以确定应用于存储器阵列的特定测试模式。 地址频率位决定在存储器阵列的每个单元上执行多少个内存周期。 在X1模式下，在任何给定的子周期内，每个单元只执行一个存储周期。 在X2模式下，对每个单元执行两个存储周期，允许单元被写入，然后在相同的子周期中读取。在X4模式下，对每个单元执行四个存储周期，而在Xg模式下，所有8位 在每个单元上使用读/写和数据，从而为存储器阵列内的每个单元产生8个存储周期。