公开(公告)号：US20080067683A1

公开(公告)日：2008-03-20

申请号：US11871533

申请日：2007-10-12

申请人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

发明人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

IPC分类号： H01L23/48

CPC分类号： H01L21/306 ,  H01L21/32135 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76865 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/00

摘要： Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

公开(公告)号：US20080066860A1

公开(公告)日：2008-03-20

申请号：US11871504

申请日：2007-10-12

申请人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

发明人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

IPC分类号： C23F1/00

CPC分类号： H01L21/306 ,  H01L21/32135 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76865 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/00

摘要： Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

摘要翻译： 公开了一种在电介质层上处理包括衬底，电介质层和TaN-Ta衬垫的类型的半导体结构的方法和系统。 该方法包括使用XeF 2将至少一部分TaN-Ta衬套完全去除到介电层的步骤。 在优选实施例中，本发明使用XeF2选择性气相蚀刻作为Ta-TaN化学机械抛光（CMP）的替代品作为基本的“衬垫去除工艺”，并且作为“选择性电镀镀层去除工艺”。 在第一次使用中，XeF2用于在铜CMP之后去除金属衬垫TaN-Ta。 在第二次使用中，XeF2蚀刻用于选择性地去除用于在铜导体上形成金属覆盖层的电镀基底（TaN-Ta）。

公开(公告)号：US20060189134A1

公开(公告)日：2006-08-24

申请号：US11064561

申请日：2005-02-24

申请人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

发明人： John Cotte ,  Nils Hoivik ,  Christopher Jahnes ,  Robert Wisnieff

IPC分类号： H01L21/44 ,  H01L23/48

CPC分类号： H01L21/306 ,  H01L21/32135 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76865 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2924/01002 ,  H01L2924/01006 ,  H01L2924/01018 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01054 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/04953 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30105 ,  H01L2924/00

摘要： Disclosed are a method and a system for processing a semiconductor structure of the type including a substrate, a dielectric layer, and a TaN—Ta liner on the dielectric layer. The method comprises the step of using XeF2 to remove at least a portion of the TaN—Ta liner completely to the dielectric layer. In the preferred embodiments, the present invention uses XeF2 selective gas phase etching as alternatives to Ta—TaN Chemical Mechanical Polishing (CMP) as a basic “liner removal process” and as a “selective cap plating base removal process.” In this first use, XeF2 is used to remove the metal liner, TaN—Ta, after copper CMP. In the second use, the XeF2 etch is used to selectively remove a plating base (TaN—Ta) that was used to form a metal cap layer over the copper conductor.

公开(公告)号：US20070194450A1

公开(公告)日：2007-08-23

申请号：US11358183

申请日：2006-02-21

申请人： Christy Tyberg ,  Katherine Saenger ,  Jack Chu ,  Harold Hovel ,  Robert Wisnieff ,  Kerry Bernstein ,  Stephen Bedell

发明人： Christy Tyberg ,  Katherine Saenger ,  Jack Chu ,  Harold Hovel ,  Robert Wisnieff ,  Kerry Bernstein ,  Stephen Bedell

IPC分类号： H01L23/52

CPC分类号： H01L23/5226 ,  H01L23/53271 ,  H01L27/124 ,  H01L27/1248 ,  H01L2924/0002 ,  H01L2924/00

摘要： This invention provides structures and a fabrication process for incorporating thin film transistors in back end of the line (BEOL) interconnect structures. The structures and fabrication processes described are compatible with processing requirements for the BEOL interconnect structures. The structures and fabrication processes utilize existing processing steps and materials already incorporated in interconnect wiring levels in order to reduce added cost associated with incorporating thin film transistors in the these levels. The structures enable vertical (3D) integration of multiple levels with improved manufacturability and reliability as compared to prior art methods of 3D integration.

摘要翻译： 本发明提供了用于在线路后端（BEOL）互连结构中并入薄膜晶体管的结构和制造工艺。 所描述的结构和制造工艺与BEOL互连结构的处理要求相兼容。 结构和制造工艺利用已经并入到互连布线层中的现有处理步骤和材料，以便降低与在这些层级中引入薄膜晶体管相关联的附加成本。 与现有技术的3D集成方法相比，该结构能够实现多层次的垂直（3D）集成，具有改进的可制造性和可靠性。

公开(公告)号：US20090023284A1

公开(公告)日：2009-01-22

申请号：US11778876

申请日：2007-07-17

申请人： Qinghuang Lin ,  Sampath Purushothaman ,  Robert Wisnieff

发明人： Qinghuang Lin ,  Sampath Purushothaman ,  Robert Wisnieff

IPC分类号： H01L21/4763 ,  C21D1/00

CPC分类号： H01L21/76802 ,  F27B17/0025 ,  H01L21/67115 ,  H01L21/67173 ,  H01L21/67225 ,  H01L21/76814 ,  H01L21/76825

摘要： The present disclosure relates to an integrated wafer processing apparatus for fabricating semiconductor chips. This integrated wafer processing system combines the lithography patterning steps and irradiation curing steps of the patternable dielectric into one system. The patternable low-k material of the present disclosure also functions as a photoresist, i.e. is a photo-patternable low-k dielectric material.

摘要翻译： 本公开涉及一种用于制造半导体芯片的集成晶片处理装置。 该集成晶片处理系统将可图案化电介质的光刻图案化步骤和照射固化步骤组合成一个系统。 本公开的可图案化的低k材料还起到光致抗蚀剂的作用，即光可图案化的低k电介质材料。

公开(公告)号：US20060220152A1

公开(公告)日：2006-10-05

申请号：US11095373

申请日：2005-03-31

申请人： Elbert Huang ,  Philip Oldiges ,  Ghavam Shahidi ,  Christy Tyberg ,  Xinlin Wang ,  Robert Wisnieff

发明人： Elbert Huang ,  Philip Oldiges ,  Ghavam Shahidi ,  Christy Tyberg ,  Xinlin Wang ,  Robert Wisnieff

IPC分类号： H01L29/78 ,  H01L21/469

CPC分类号： H01L29/4991 ,  H01L29/4983 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： Disclosed is a MOSFET structure and method of fabricating the structure that incorporates a multi-layer sidewall spacer to suppress parasitic overlap capacitance between the gate conductor and the source/drain extensions without degrading drive current and, thereby, effecting overall MOSFET performance. In one embodiment, the multi-layer sidewall spacer is formed with a gap layer having a dielectric constant equal to one and a permeable low-K (e.g., less than 3.5) dielectric layer. In another embodiment, the multi-layer sidewall spacer is formed with a first L-shaped dielectric layer having a permittivity value of less than approximately three and a second dielectric layer. Either embodiment may also have a third nitride or oxide spacer layer. This third spacer layer provides increased structural integrity.

摘要翻译： 公开了一种MOSFET结构和制造该结构的方法，该结构包括多层侧壁间隔物以抑制栅极导体和源/漏扩展之间的寄生重叠电容，而不降低驱动电流，从而影响整体MOSFET的性能。 在一个实施例中，多层侧壁间隔物形成有具有等于1的介电常数的间隙层和可渗透的低K（例如，小于3.5）的电介质层。 在另一个实施例中，多层侧壁间隔物形成有介电常数值小于约三的第一L形介电层和第二介电层。 任一实施例也可以具有第三氮化物或氧化物隔离层。 该第三间隔层提供增加的结构完整性。

公开(公告)号：US07811923B2

公开(公告)日：2010-10-12

申请号：US11778876

申请日：2007-07-17

申请人： Qinghuang Lin ,  Sampath Purushothaman ,  Robert Wisnieff

发明人： Qinghuang Lin ,  Sampath Purushothaman ,  Robert Wisnieff

IPC分类号： H01L21/4763

CPC分类号： H01L21/76802 ,  F27B17/0025 ,  H01L21/67115 ,  H01L21/67173 ,  H01L21/67225 ,  H01L21/76814 ,  H01L21/76825

摘要： The present disclosure relates to an integrated wafer processing apparatus for fabricating semiconductor chips. This integrated wafer processing system combines the lithography patterning steps and irradiation curing steps of the patternable dielectric into one system. The patternable low-k material of the present disclosure also functions as a photoresist, i.e. is a photo-patternable low-k dielectric material.

摘要翻译： 本公开涉及一种用于制造半导体芯片的集成晶片处理装置。 该集成晶片处理系统将可图案化电介质的光刻图案化步骤和照射固化步骤组合成一个系统。 本公开的可图案化的低k材料还起到光致抗蚀剂的作用，即光可图案化的低k电介质材料。

公开(公告)号：US20060278895A1

公开(公告)日：2006-12-14

申请号：US11152750

申请日：2005-06-14

申请人： Geoffrey Burr ,  Chandrasekharan Kothandaraman ,  Chung Lam ,  Xiao Liu ,  Stephen Rossnagel ,  Christy Tyberg ,  Robert Wisnieff

发明人： Geoffrey Burr ,  Chandrasekharan Kothandaraman ,  Chung Lam ,  Xiao Liu ,  Stephen Rossnagel ,  Christy Tyberg ,  Robert Wisnieff

IPC分类号： H01L27/10 ,  H01L29/73

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。

公开(公告)号：US20050045889A1

公开(公告)日：2005-03-03

申请号：US10890759

申请日：2004-07-14

申请人： Peter Fryer ,  Robert Wisnieff ,  Takatoshi Tsujimura

发明人： Peter Fryer ,  Robert Wisnieff ,  Takatoshi Tsujimura

IPC分类号： G02F1/1335 ,  G02F1/1362 ,  G02F1/1368 ,  H01L21/288 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786 ,  H01L29/04

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L27/1292 ,  H01L29/41733 ,  H01L29/66757 ,  H01L29/78609 ,  H01L29/78633 ,  H01L29/78666

摘要： The present invention is directed to a thin film transistor (and related multilayer structures) that includes: source and drain electrodes 14 and 15 disposed at a specified interval above an insulating substrate 11 and formed by printing-and-plating; an a-Si film 16 disposed for the source and drain electrodes 14 and 15; a gate insulating film 17 laminated on the a-Si film 16; and a gate electrode 18 laminated on the gate insulating film 17 and formed by printing-and-plating. The a-Si film 16 and the gate insulating film 17 have an offset region 20 that uniformly extends beyond the dimensions of the gate electrode 18.

摘要翻译： 本发明涉及一种薄膜晶体管（及相关的多层结构），其包括：以绝缘基板11上方的特定间隔设置并通过印刷和电镀形成的源极和漏极14和15; 为源极和漏极14和15设置的a-Si膜16; 层叠在a-Si膜16上的栅极绝缘膜17; 以及层叠在栅极绝缘膜17上并通过印刷和电镀形成的栅电极18。 a-Si膜16和栅极绝缘膜17具有均匀地延伸超过栅电极18的尺寸的偏移区域20。

公开(公告)号：US20070290233A1

公开(公告)日：2007-12-20

申请号：US11844109

申请日：2007-08-23

申请人： Geoffrey Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen Rossnagel ,  Christy Tyberg ,  Robert Wisnieff

发明人： Geoffrey Burr ,  Chandrasekharan Kothandaraman ,  Chung Hon Lam ,  Xiao Hu Liu ,  Stephen Rossnagel ,  Christy Tyberg ,  Robert Wisnieff

IPC分类号： H01L27/10 ,  H01L21/44

CPC分类号： H01L23/5256 ,  H01L23/5252 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1286 ,  H01L45/1293 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A reversible fuse structure in an integrated circuit is obtained through the implementation of a fuse cell having a short thin line of phase change materials in contact with via and line structures capable of passing current through the line of phase change material (fuse cell). The current is passed through the fuse cell in order to change the material from a less resistive material to a more resistive material through heating the phase change material in the crystalline state to the melting point then quickly quenching the material into the amorphous state. The reversible programming is achieved by passing a lower current through the fuse cell to convert the high resistivity amorphous material to a lower resistivity crystalline material. Appropriate sense-circuitry is integrated to read the information stored in the fuses, wherein said sense circuitry is used to enable or disable circuitry.

摘要翻译： 集成电路中的可逆熔丝结构通过实现具有短路相变材料的熔断电池获得，所述相变材料与能够使电流通过相变材料线（熔丝电池）的通孔和线结构相接触。 电流通过熔丝电池，以便通过将结晶状态的相变材料加热至熔点，从而将材料从较小电阻的材料转变为更电阻的材料，然后快速将材料淬火成非晶状态。 可逆编程通过使较低电流通过熔丝电池来实现，以将高电阻率无定形材料转换成较低电阻率的晶体材料。 集成适当的感测电路以读取存储在熔丝中的信息，其中所述感测电路用于启用或禁用电路。