公开(公告)号：US07029944B1

公开(公告)日：2006-04-18

申请号：US10956789

申请日：2004-09-30

申请人： John F. Conley, Jr. ,  Yoshi Ono ,  Wei Gao ,  David R. Evans

发明人： John F. Conley, Jr. ,  Yoshi Ono ,  Wei Gao ,  David R. Evans

IPC分类号： H01L21/00

CPC分类号： H01L21/31053 ,  H01L21/31133 ,  H01L27/14627 ,  H01L27/14685

摘要： A method of forming a microlens structure is provided along with a CCD array structure employing a microlens array. An embodiment of the method comprises providing a substrate having a surface with photo-elements on the surface; depositing a transparent material overlying the surface of the substrate; depositing a CMP stop overlying the transparent material; depositing a lens-shaping layer overlying the CMP stop layer; depositing and patterning a photoresist layer overlying the lens-shaping layer to form openings to expose the lens-shaping layer; introducing a first isotropic etchant into the openings and etching the lens-shaping layer where exposed to form initial lens shapes having a radius; stripping the photoresist; exposing the lens-shaping layer to a second isotropic etchant to increase the radius of the lens shapes; transferring the lens shape through the CMP stop layer into the transparent material using an anisotropic etch; and depositing a lens material overlying the transparent material, whereby the lens shapes are at least partially filled with lens material. Planarizing the lens material using CMP and stopping at the CMP stop layer.

摘要翻译： 提供一种形成微透镜结构的方法以及采用微透镜阵列的CCD阵列结构。 该方法的一个实施例包括提供具有在表面上具有光元件的表面的基底; 沉积覆盖衬底表面的透明材料; 沉积覆盖透明材料的CMP停止点; 沉积覆盖CMP停止层的透镜成形层; 沉积和图案化覆盖透镜成形层的光致抗蚀剂层以形成露出透镜成形层的开口; 在开口中引入第一各向同性蚀刻剂并蚀刻暴露于其中形成具有半径的初始透镜形状的透镜成形层; 剥离光刻胶; 将透镜成形层暴露于第二各向同性蚀刻剂以增加透镜形状的半径; 使用各向异性蚀刻将透镜形状通过CMP停止层转移到透明材料中; 以及沉积覆盖透明材料的透镜材料，由此透镜形状至少部分地被透镜材料填充。 使用CMP对透镜材料进行平面化，并在CMP停止层处停止。

公开(公告)号：US07160819B2

公开(公告)日：2007-01-09

申请号：US11114862

申请日：2005-04-25

申请人： John F. Conley, Jr. ,  Yoshi Ono ,  David R. Evans

发明人： John F. Conley, Jr. ,  Yoshi Ono ,  David R. Evans

IPC分类号： H01L21/31

CPC分类号： H01L21/0228 ,  C23C16/042 ,  C23C16/407 ,  C23C16/45525 ,  H01L21/0217 ,  H01L21/02175 ,  H01L21/02334 ,  H01L21/0234 ,  H01L21/3141

摘要： A method for selective ALD of ZnO on a wafer preparing a silicon wafer; patterning the silicon wafer with a blocking agent in selected regions where deposition of ZnO is to be inhibited, wherein the blocking agent is taken from a group of blocking agents includes isopropyl alcohol, acetone and deionized water; depositing a layer of ZnO on the wafer by ALD using diethyl zinc and H2O at a temperature of between about 140° C. to 170° C.; and removing the blocking agent from the wafer.

摘要翻译： 在准备硅晶片的晶片上的ZnO的选择性ALD的方法; 在其中要抑制ZnO沉积的选定区域中用封闭剂对硅晶片进行图案化，其中封闭剂取自一组封闭剂，包括异丙醇，丙酮和去离子水; 在约140℃至170℃的温度下，使用二乙基锌和H 2 O 2，通过ALD在晶片上沉积ZnO层。 并从晶片上除去封闭剂。

公开(公告)号：US07589464B2

公开(公告)日：2009-09-15

申请号：US11070051

申请日：2005-03-01

申请人： John F. Conley, Jr. ,  David R. Evans ,  Wei Gao ,  Yoshi Ono

发明人： John F. Conley, Jr. ,  David R. Evans ,  Wei Gao ,  Yoshi Ono

IPC分类号： H05B33/26

CPC分类号： H05B33/10 ,  B82Y20/00 ,  C09K11/54 ,  C09K11/642 ,  H01L33/18 ,  H05B33/14

摘要： A device and a fabrication method are provided for an EL device with a nanotip-contoured phosphor layer. The method comprises: forming a bottom electrode with nanotips; forming a phosphor layer overlying the bottom electrode, having irregularly-shaped top and bottom surfaces; and, forming a top electrode overlying the phosphor layer. The bottom electrode top surface has a nanotip contour, and the phosphor layer irregularly-shaped top and bottom surfaces have contours approximately matching the bottom electrode top surface nanotip contour. In one aspect, a contoured bottom dielectric is interposed between the bottom electrode and the phosphor layer, having top and bottoms surfaces with contours approximately matching the nanotip contour. Likewise, a top dielectric may be interposed between the top electrode and the phosphor layer, having a bottom surface with a contour approximately matching the contour of phosphor layer top surface.

摘要翻译： 提供了一种具有纳米尺度荧光体层的EL器件的器件和制造方法。 该方法包括：形成具有纳米尖端的底部电极; 形成覆盖在底部电极上的荧光体层，具有不规则形状的顶部和底部表面; 并且形成覆盖磷光体层的顶部电极。 底部电极顶表面具有纳米尖端轮廓，并且荧光体层不规则形状的顶表面和底表面具有与底部电极顶表面纳米尖端轮廓近似匹配的轮廓。 在一个方面，在底部电极和荧光体层之间插入有轮廓的底部电介质，其具有顶部和底部表面，轮廓几乎与纳米尖端轮廓相匹配。 类似地，顶部电介质可以插入在顶部电极和荧光体层之间，具有大致与荧光体层顶表面的轮廓相匹配的轮廓的底面。

公开(公告)号：US06200866B1

公开(公告)日：2001-03-13

申请号：US09410346

申请日：1999-09-30

申请人： Yanjun Ma ,  Douglas J. Tweet ,  David R. Evans ,  Yoshi Ono

发明人： Yanjun Ma ,  Douglas J. Tweet ,  David R. Evans ,  Yoshi Ono

IPC分类号： H01L21338

CPC分类号： H01L21/31053 ,  H01L21/2807 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/76801 ,  H01L21/76804 ,  H01L21/76834 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/4908 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66772 ,  H01L29/78684

摘要： A method of fabricating a MOSFET is provided, including: depositing an oxide layer on a silicon substrate for device isolation; forming a silicon based alloy island above a gate region in the substrate, wherein the silicon based alloy comprises a silicon germanium alloy or a silicon tin alloy or another alloy of Group IV-B elements; building a sidewall about the silicon based alloy island; forming a source region and a drain region in the substrate; removing the silicon based alloy island, thereby leaving a void over the gate region; filing the void and the areas over the source region and the drain region; and planarizing the upper surface of the structure by chemical mechanical polishing. Alternative embodiments providing conventional and raised source/drain structures are disclosed.

摘要翻译： 提供一种制造MOSFET的方法，包括：在硅衬底上沉积氧化层用于器件隔离; 在所述基板的栅极区域的上方形成硅基合金岛，其中所述硅基合金包含硅锗合金或硅锡合金或第IV-B族元素的另一种合金; 围绕硅基合金岛构建侧壁; 在衬底中形成源区和漏区; 去除硅基合金岛，从而在栅极区域上留下空隙; 填充空隙和源区域和漏区域上的区域; 并通过化学机械抛光对结构的上表面进行平面化。 公开了提供常规和凸起的源极/漏极结构的替代实施例。

公开(公告)号：US07364989B2

公开(公告)日：2008-04-29

申请号：US11174350

申请日：2005-07-01

申请人： Douglas J. Tweet ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

发明人： Douglas J. Tweet ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/20

CPC分类号： H01L21/02192 ,  H01L21/02197 ,  H01L21/0228 ,  H01L21/3147

摘要： A method of controlling strain in a single-crystal, epitaxial oxide film, includes preparing a silicon substrate; forming a silicon alloy layer taken from the group of silicon alloy layer consisting of Si1-xGex and Si1-yCy on the silicon substrate; adjusting the lattice constant of the silicon alloy layer by selecting the alloy material content to adjust and to select a type of strain for the silicon alloy layer; depositing a single-crystal, epitaxial oxide film, by atomic layer deposition, taken from the group of oxide films consisting of perovskite manganite materials, single crystal rare-earth oxides and perovskite oxides, not containing manganese; and rare earth binary and ternary oxides, on the silicon alloy layer; and completing a desired device.

摘要翻译： 一种控制单晶外延氧化膜中的应变的方法包括制备硅衬底; 从由Si 1-x Ge x Si和Si 1-y C C组成的硅合金层组形成硅合金层 > y ; 通过选择合金材料含量来调整硅合金层的晶格常数，并选择一种用于硅合金层的应变; 从由不含锰的钙钛矿亚锰酸盐材料，单晶稀土氧化物和钙钛矿氧化物组成的氧化膜组中，通过原子层沉积法沉积单晶外延氧化膜; 和稀土二元和三元氧化物，在硅合金层上; 并完成所需的设备。

公开(公告)号：US08264081B2

公开(公告)日：2012-09-11

申请号：US11311546

申请日：2005-12-19

申请人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L23/48 ,  H01L23/52

CPC分类号： H01L21/28562 ,  H01L21/76841 ,  H01L2221/1078

摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

摘要翻译： 通过原子层化学气相沉积（ALCVD）将多层阻挡金属薄膜沉积在衬底上。 多层膜可以包括单个化学物质的几个不同层，或者各个不同的或交替的化学物质的几个层。 在优选实施例中，多层阻挡薄膜包括在衬底上的氮化钽层，其上沉积有氮化钛层。 整个多层膜的厚度可以是大约50埃。 当与通过常规化学气相沉积（CVD）沉积的膜相比时，该膜具有优异的膜特性，例如抗扩散能力，低电阻率，高密度和台阶覆盖。 本发明的多层阻挡金属薄膜具有改善的粘合特性，特别适用于其上的铜膜的金属化。

公开(公告)号：US07015138B2

公开(公告)日：2006-03-21

申请号：US09819296

申请日：2001-03-27

申请人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei Pan ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/44

CPC分类号： H01L21/28562 ,  H01L21/76841 ,  H01L2221/1078

摘要： A multi-layered barrier metal thin film is deposited on a substrate by atomic layer chemical vapor deposition (ALCVD). The multi-layer film may comprise several different layers of a single chemical species, or several layers each of distinct or alternating chemical species. In a preferred embodiment, the multi-layer barrier thin film comprises a Tantalum Nitride layer on a substrate, with a Titanium Nitride layer deposited thereon. The thickness of the entire multi-layer film may be approximately fifty Angstroms. The film has superior film characteristics, such as anti-diffusion capability, low resistivity, high density, and step coverage, when compared to films deposited by conventional chemical vapor deposition (CVD). The multi-layered barrier metal thin film of the present invention has improved adhesion characteristics and is particularly suited for metallization of a Copper film thereon.

公开(公告)号：US06573134B2

公开(公告)日：2003-06-03

申请号：US09817834

申请日：2001-03-27

申请人： Yanjun Ma ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

发明人： Yanjun Ma ,  Yoshi Ono ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L218238

CPC分类号： H01L21/823842 ,  H01L27/092

摘要： A method of fabricating a dual metal gate CMOS includes forming a gate oxide in a gate region and depositing a place-holder gate in each of a n-well and p-well; removing the place-holder gate and gate oxide; depositing a high-k dielectric in the gate region; depositing a first metal in the gate region of the p-well; depositing a second metal in the gate region of each of the n-well and p-well; and insulating and metallizing the structure. A dual metal gate CMOS of the invention includes PMOS transistor and a NMOS transistor. In the NMOS, a gate includes a high-k cup, a first metal cup formed in the high-k cup, and a second metal gate formed in the first metal cup. In the PMOS, a gate includes a high-k cup and a second metal gate formed in the high-k cup.

公开(公告)号：US20120302743A1

公开(公告)日：2012-11-29

申请号：US13117529

申请日：2011-05-27

申请人： Sean Andrew Vail ,  David R. Evans ,  Wei Pan

发明人： Sean Andrew Vail ,  David R. Evans ,  Wei Pan

IPC分类号： C07D487/22

CPC分类号： C07D487/22 ,  Y02E10/542

摘要： A long wavelength absorbing porphyrin/metalloporphyrin molecule is provided, made up of a porphyrin macrocycle and an anchor group for attachment to a substrate. A molecular linking element is interposed between the porphyrin macrocycle and the anchor group. The porphyrin/metalloporphyrin molecule also includes an (aminophenyl)amine group, either N,N-(4-aminophenyl)amine or N-phenyl-N-(4-aminophenyl)amine, where an amino moiety of the 4-aminophenyl group is derivatized by an element such as hydrogen, haloalkanes, aromatic hydrocarbons, halogenated aromatic hydrocarbons, heteroarenes, halogenated heteroarenes, or combinations of the above-mentioned elements.

摘要翻译： 提供长波长吸收卟啉/金属卟啉分子，其由卟啉大环化合物和锚定基团组成，用于附着于基底。 分子连接元件介于卟啉大环和锚基之间。 卟啉/金属卟啉分子还包括（氨基苯基）胺基团，N，N-（4-氨基苯基）胺或N-苯基-N-（4-氨基苯基）胺，其中4-氨基苯基的氨基部分为 由诸如氢，卤代烷烃，芳族烃，卤代芳烃，杂芳烃，卤代杂芳烃或上述元素的组合的元素衍生。

公开(公告)号：US07968419B2

公开(公告)日：2011-06-28

申请号：US12234663

申请日：2008-09-21

申请人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

发明人： Tingkai Li ,  Sheng Teng Hsu ,  David R. Evans

IPC分类号： H01L21/20

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C2213/31 ,  H01L27/2409 ,  H01L29/66143 ,  H01L29/872 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method is provided for forming a metal/semiconductor/metal (MSM) back-to-back Schottky diode from a silicon (Si) semiconductor. The method deposits a Si semiconductor layer between a bottom electrode and a top electrode, and forms a MSM diode having a threshold voltage, breakdown voltage, and on/off current ratio. The method is able to modify the threshold voltage, breakdown voltage, and on/off current ratio of the MSM diode in response to controlling the Si semiconductor layer thickness. Generally, both the threshold and breakdown voltage are increased in response to increasing the Si thickness. With respect to the on/off current ratio, there is an optimal thickness. The method is able to form an amorphous Si (a-Si) and polycrystalline Si (polySi) semiconductor layer using either chemical vapor deposition (CVD) or DC sputtering. The Si semiconductor can be doped with a Group V donor material, which decreases the threshold voltage and increases the breakdown voltage.

摘要翻译： 提供了用于从硅（Si）半导体形成金属/半导体/金属（MSM）背对背肖特基二极管的方法。 该方法在底电极和顶电极之间沉积Si半导体层，并形成具有阈值电压，击穿电压和开/关电流比的MSM二极管。 响应于控制Si半导体层厚度，该方法能够修改MSM二极管的阈值电压，击穿电压和导通/截止电流比。 通常，响应于Si厚度的增加，阈值和击穿电压都增加。 关于开/关电流比，存在最佳厚度。 该方法能够使用化学气相沉积（CVD）或DC溅射形成非晶Si（a-Si）和多晶硅（polySi）半导体层。 Si半导体可以掺杂有V族施主材料，其降低阈值电压并增加击穿电压。