公开(公告)号：US20050116357A1

公开(公告)日：2005-06-02

申请号：US10906189

申请日：2005-02-08

申请人： John Fitzsimmons ,  Stephen Gates ,  Michael Lane ,  Eric Liniger

发明人： John Fitzsimmons ,  Stephen Gates ,  Michael Lane ,  Eric Liniger

IPC分类号： H01L21/44 ,  H01L21/4763 ,  H01L21/48 ,  H01L21/50 ,  H01L23/00 ,  H01L23/28

CPC分类号： H01L23/564 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method is disclosed of repairing wirebond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-k dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.

摘要翻译： 公开了一种修复半导体芯片（例如高速半导体微处理器，专用集成电路（ASIC））和其它高速集成电路器件（特别是使用低k电介质材料的器件）的引线键合损坏的方法。 该方法涉及使用反应性液体的表面改性。 在优选的实施方案中，该方法包括将诸如TEOS的含硅液体试剂前体施加到芯片的表面，并允许液体试剂与水分反应形成固体电介质塞或膜（50）以产生抵抗 湿度进入，从而提高这种半导体器件的温度/湿度/偏差（THB）性能。

公开(公告)号：US20080079176A1

公开(公告)日：2008-04-03

申请号：US11954966

申请日：2007-12-12

申请人： John Fitzsimmons ,  Stephen Gates ,  Michael Lane ,  Eric Liniger

发明人： John Fitzsimmons ,  Stephen Gates ,  Michael Lane ,  Eric Liniger

IPC分类号： H01L23/49

CPC分类号： H01L23/564 ,  H01L24/05 ,  H01L24/48 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05554 ,  H01L2224/05556 ,  H01L2224/05624 ,  H01L2224/48463 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method is disclosed of repairing wirebond damage on semiconductor chips such as high speed semiconductor microprocessors, application specific integrated circuits (ASICs), and other high speed integrated circuit devices, particularly devices using low-k dielectric materials. The method involves surface modification using reactive liquids. In a preferred embodiment, the method comprises applying a silicon-containing liquid reagent precursor such as TEOS to the surface of the chip and allowing the liquid reagent to react with moisture to form a solid dielectric plug or film (50) to produce a barrier against moisture ingress, thereby enhancing the temperature/humidity/bias (THB) performance of such semiconductor devices.

摘要翻译： 公开了一种修复半导体芯片（例如高速半导体微处理器，专用集成电路（ASIC））和其它高速集成电路器件（特别是使用低k电介质材料的器件）的引线键合损伤的方法。 该方法涉及使用反应性液体的表面改性。 在优选的实施方案中，该方法包括将诸如TEOS的含硅液体试剂前体施加到芯片的表面，并允许液体试剂与水分反应形成固体电介质塞或膜（50）以产生抵抗 湿度进入，从而提高这种半导体器件的温度/湿度/偏差（THB）性能。

公开(公告)号：US20080044668A1

公开(公告)日：2008-02-21

申请号：US11034479

申请日：2005-01-13

申请人： Christos Dimitrakopoulos ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Eric Liniger ,  Xiao Liu ,  Son Nguyen ,  Deborah Neumayer ,  Thomas Shaw

发明人： Christos Dimitrakopoulos ,  Stephen Gates ,  Alfred Grill ,  Michael Lane ,  Eric Liniger ,  Xiao Liu ,  Son Nguyen ,  Deborah Neumayer ,  Thomas Shaw

IPC分类号： B32B9/04 ,  B32B13/04

CPC分类号： H01L21/76834 ,  C23C16/30 ,  C23C16/56 ,  H01L21/02126 ,  H01L21/02203 ,  H01L21/02274 ,  H01L21/02282 ,  H01L21/02348 ,  H01L21/3105 ,  H01L21/31058 ,  H01L21/31633 ,  H01L21/76801 ,  H01L21/76825 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76832 ,  Y10T428/249953 ,  Y10T428/249969 ,  Y10T428/249979

摘要： A method for forming a ultralow dielectric constant layer with controlled biaxial stress is described incorporating the steps of forming a layer containing Si, C, O and H by one of PECVD and spin-on coating and curing the film in an environment containing very low concentrations of oxygen and water each less than 10 ppm. A material is also described by using the method with a dielectric constant of not more than 2.8. The invention overcomes the problem of forming films with low biaxial stress less than 46 MPa.

摘要翻译： 描述了形成具有受控双轴应力的超低介电常数层的方法，其包括以下步骤：通过PECVD和旋涂方法之一形成包含Si，C，O和H的层，并在含有非常低的浓度的环境中固化该膜 的氧和水各自小于10ppm。 还通过使用介电常数不大于2.8的方法描述材料。 本发明克服了低双轴应力低于46MPa的薄膜形成问题。

公开(公告)号：US20060202311A1

公开(公告)日：2006-09-14

申请号：US10906815

申请日：2005-03-08

申请人： Son Nguyen ,  Sarah Lane ,  Eric Liniger ,  Kensaku Ida ,  Darryl Restaino

发明人： Son Nguyen ,  Sarah Lane ,  Eric Liniger ,  Kensaku Ida ,  Darryl Restaino

IPC分类号： H01L23/58 ,  H01L21/469 ,  H01L23/52

CPC分类号： H01L21/76801 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0234 ,  H01L21/02348 ,  H01L21/02351 ,  H01L21/02354 ,  H01L21/3105 ,  H01L21/31633 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/76829 ,  H01L21/76834 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.

摘要翻译： 具有约3.0或更小的有效介电常数k的低k电介质堆叠，其中通过将至少一个纳米层引入电介质叠层来提高堆叠的机械性能。 在不显着增加叠层内的膜的介电常数并且不需要使本发明的电介质叠层进行任何后处理步骤的情况下，实现机械性能的改善。 具体地，本发明提供了一种低k电介质堆叠，其包含至少一个低k​​电介质材料和存在于至少一个低k​​电介质材料内的至少一个纳米层。

公开(公告)号：US20060160350A1

公开(公告)日：2006-07-20

申请号：US11037970

申请日：2005-01-18

申请人： John Bruley ,  Roy Carruthers ,  Lynne Gignac ,  Chao-Kun Hu ,  Eric Liniger ,  Sandra Malhotra ,  Stephen Rossnagel

发明人： John Bruley ,  Roy Carruthers ,  Lynne Gignac ,  Chao-Kun Hu ,  Eric Liniger ,  Sandra Malhotra ,  Stephen Rossnagel

IPC分类号： H01L21/4763

CPC分类号： H01L21/76849 ,  H01L21/76829 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.

摘要翻译： 公开了在沉积层间电介质或电介质扩散阻挡层之前，通过1-5nm厚的元件涂覆Cu镶嵌线的自由表面的步骤。 涂层提供防氧化保护，增加Cu和介电层之间的粘合强度，并减少Cu的界面扩散。 此外，薄盖层进一步增加电迁移Cu寿命，并减少应力引起的空隙。 选择元件可以直接沉积在嵌入在下层电介质中的Cu上，而不会在Cu线之间引起电短路。 这些选择的元素是基于它们具有氧和水的高的负还原电位，以及与Cu的化合物的低溶解度和形成。