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    Optimized device isolation
    1.
    发明授权
    Optimized device isolation 有权
    优化设备隔离

    公开(公告)号：US07868423B2

    公开(公告)日：2011-01-11

    申请号：US12269073

    申请日：2008-11-12

    申请人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

    发明人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St. Onge ,  James A. Slinkman

    IPC分类号： H01L21/02

    CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928

    摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

    摘要翻译： 用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。 该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。 一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域之上，并且在所有p-阱区下面， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。 隔离MOSFET的n阱连接到深n波段区域。 所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

    Optimized Device Isolation
    2.
    发明申请
    Optimized Device Isolation 有权
    优化设备隔离

    公开(公告)号：US20100117122A1

    公开(公告)日：2010-05-13

    申请号：US12269073

    申请日：2008-11-12

    申请人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St Onge ,  James A. Slinkman

    发明人： John J. Benoit ,  David S. Collins ,  Natalie B. Feilchenfeld ,  Michael L. Gautsch ,  Xuefeng Liu ,  Robert M. Rassel ,  Stephen A. St Onge ,  James A. Slinkman

    IPC分类号： H01L27/092 ,  H01L27/085

    CPC分类号： H01L21/761 ,  H01L21/823481 ,  H01L21/823493 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/0921 ,  H01L27/0928

    摘要： A structure for a semiconductor device includes an isolated MOSFET (e.g., NFET) having triple-well technology adjacent to an isolated PFET which itself is adjacent to an isolated NFET. The structure includes a substrate in which is formed a deep n-band region underneath any n-wells, p-wells and p-band regions within the substrate. One p-band region is formed above the deep n-band region and underneath the isolated p-well for the isolated MOSFET, while another p-band region is formed above the deep n-band region and underneath all of the p-wells and n-wells, including those that are part of the isolated PFET and NFET devices within the substrate. The n-wells for the isolated MOSFET are connected to the deep n-band region. The resulting structure provides for improved device isolation and reduction of noise propagating from the substrate to the FETs while maintaining the standard CMOS spacing layout spacing rules and electrical biasing characteristics both external and internal to the triple-well isolation regions.

    摘要翻译： 用于半导体器件的结构包括具有三阱技术的隔离MOSFET（例如，NFET），其邻近隔离PFET，其本身与隔离的NFET相邻。 该结构包括其中在衬底内的任何n阱，p阱和p带区之下形成深n波段区的衬底。 一个p带区域形成在深n波段区域之上，隔离的MOSFET的隔离p阱下面，而另一个p波段区域形成在深n波段区域上方，并在所有p阱区域下方， n阱，包括作为衬底内的隔离PFET和NFET器件的一部分的n阱。 隔离MOSFET的n阱连接到深n波段区域。 所得到的结构提供改进的器件隔离和降低从衬底传播到FET的噪声，同时保持三阱隔离区域的外部和内部的标准CMOS间隔布局间隔规则和电偏置特性。

    Structure and method for enhanced triple well latchup robustness
    7.
    发明授权
    Structure and method for enhanced triple well latchup robustness 有权
    增强三井闭锁鲁棒性的结构和方法

    公开(公告)号：US07442996B2

    公开(公告)日：2008-10-28

    申请号：US11275644

    申请日：2006-01-20

    申请人： David S. Collins ,  James A. Slinkman ,  Steven H. Voldman

    发明人： David S. Collins ,  James A. Slinkman ,  Steven H. Voldman

    IPC分类号： H01L29/76

    CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L27/0921 ,  H01L29/1087

    摘要： Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p− substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

    摘要翻译： 公开了一种三阱CMOS器件结构，其通过在p阱下面添加n +掩埋层来解决闭锁的问题，以将p阱与p-衬底隔离，但也在n阱下方。 该结构通过将n +掩埋层延伸到整个器件的下方来消除n阱和n +掩埋层之间的间隔问题。 该结构还通过在n +掩埋层下方的整个器件下方或仅在器件的p阱侧下面的p +掩埋层提供阈值电压散射的问题，仅在n +掩埋层之下或之上）锁存稳健性可以进一步 通过将在n +掩埋层和n阱之间消除侧向pnp，npn或pnpn器件和/或子集电极区域的隔离结构结合到器件中来改进。

    STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS
    8.
    发明申请
    STRUCTURE AND METHOD FOR ENHANCED TRIPLE WELL LATCHUP ROBUSTNESS 审中-公开
    结构和方法，增强三重保护锁定稳定性

    公开(公告)号：US20080265333A1

    公开(公告)日：2008-10-30

    申请号：US12169667

    申请日：2008-07-09

    申请人： David S. Collins ,  James A. Slinkman ,  Steven H. Voldman

    发明人： David S. Collins ,  James A. Slinkman ,  Steven H. Voldman

    IPC分类号： H01L27/06

    CPC分类号： H01L27/0928 ,  H01L21/761 ,  H01L27/0921 ,  H01L29/1087

    摘要： Disclosed is a triple well CMOS device structure that addresses the issue of latchup by adding an n+ buried layer not only beneath the p-well to isolate the p-well from the p-substrate but also beneath the n-well. The structure eliminates the spacing issues between the n-well and n+ buried layer by extending the n+ buried layer below the entire device. The structure also addresses the issue of threshold voltage scattering by providing a p+ buried layer below the entire device under the n+ buried layer or below the p-well side of the device only either under or above the n+ buried layer) Latchup robustness can further be improved by incorporating into the device an isolation structure that eliminates lateral pnp, npn, or pnpn devices and/or a sub-collector region between the n+ buried layer and the n-well.

    摘要翻译： 公开了一种三阱CMOS器件结构，其通过在p阱下面添加n +掩埋层来解决闭锁的问题，以将p阱与p衬底隔离以及在n阱下方。 该结构通过将n +掩埋层延伸到整个器件的下方来消除n阱和n +掩埋层之间的间隔问题。 该结构还通过在n +掩埋层下方的整个器件下方或仅在器件的p阱侧下面的p +掩埋层提供阈值电压散射的问题，仅在n +掩埋层之下或之上）锁存稳健性可以进一步 通过将在n +掩埋层和n阱之间消除侧向pnp，npn或pnpn器件和/或子集电极区域的隔离结构结合到器件中来改进。

    Asymmetric junction field effect transistor
    9.
    发明授权
    Asymmetric junction field effect transistor 有权
    非对称结场效应晶体管

    公开(公告)号：US07943445B2

    公开(公告)日：2011-05-17

    申请号：US12388586

    申请日：2009-02-19

    申请人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    发明人： Frederick G. Anderson ,  David S. Collins ,  Richard A. Phelps ,  Robert M. Rassel ,  Michael J. Zierak

    IPC分类号： H01L21/00 ,  H01L21/336

    CPC分类号： H01L29/1058 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/0843 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/20 ,  H01L29/22 ,  H01L29/66901 ,  H01L29/808

    摘要： A junction field effect transistor (JFET) in a semiconductor substrate includes a source region, a drain region, a channel region, an upper gate region, and a lower gate region. The lower gate region is electrically connected to the upper gate region. The upper and lower gate regions control the current flow through the channel region. By performing an ion implantation step that extends the thickness of the source region to a depth greater than the thickness of the drain region, an asymmetric JFET is formed. The extension of depth of the source region relative to the depth of the drain region reduces the length for minority charge carriers to travel through the channel region, reduces the on-resistance of the JFET, and increases the on-current of the JFET, thereby enhancing the overall performance of the JFET without decreasing the allowable Vds or dramatically increasing Voff/Vpinch.

    摘要翻译： 半导体衬底中的结型场效应晶体管（JFET）包括源极区，漏极区，沟道区，上部栅极区域和下部栅极区域。 下栅极区域电连接到上栅极区域。 上下栅极区域控制通过沟道区域的电流。 通过执行将源极区域的厚度延伸到大于漏极区域的厚度的深度的离子注入步骤，形成非对称JFET。 源极区域相对于漏极区域的深度的深度的扩展减小了少数电荷载流子穿过沟道区域的长度，减小了JFET的导通电阻，并增加了JFET的导通电流，由此 提高JFET的整体性能，而不会降低容许的Vds或显着增加Voff / Vpinch。