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1.发明授权
公开(公告)号：US5422288A
公开(公告)日：1995-06-06
申请号：US246307
申请日：1994-05-19
IPC分类号： H01L21/336 , H01L21/8234 , H01L29/08 , H01L29/10 , H01L29/739 , H01L29/78 , H01L21/265
CPC分类号： H01L29/66712 , H01L21/8234 , H01L29/1095 , H01L29/7395 , H01L29/7802 , H01L29/0847
摘要： A MOS-gated semiconductor device may be manufactured by a process in which the neck region of the device is doped through a previously deposited polysilicon gate. In the method of the present invention, the dopant in the neck region of the device is not subjected to the same temperature history as the body dopant, thereby providing means to increase the ruggedness of the device and providing means by which the threshold voltage of the device may be controlled.
摘要翻译： MOS门控半导体器件可以通过其中器件的颈区通过先前沉积的多晶硅栅极掺杂的工艺来制造。 在本发明的方法中，器件的颈部区域中的掺杂剂不会受到与体掺杂物相同的温度历史的影响，从而提供了增加器件耐用性的手段，并提供了将器件的阈值电压 设备可以被控制。
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公开(公告)号：US5095343A
公开(公告)日：1992-03-10
申请号：US609054
申请日：1990-11-06
IPC分类号： H01L29/06 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/7395
摘要： A VDMOS device includes a wafer of semiconductor material having first and second opposed major surfaces. A drain region of a first conductivity type extends along the one major surface. A plurality of body regions of a second conductivity type is in the body region at the one major surface. Each body region forms with the drain region a body/drain PN junction, the intersection of which with the first major surface is in a closed path, preferably a hexagon. A plurality of spaced source regions of the one conductivity type are in each of the body regions with each source region being positioned opposite the space between two source regions in the adjacent body region. Each source region forms with the body region a source/body PN junction. A portion of each of the source/body PN junctions is adjacent to but spaced from its respective drain/body PN junction to form a channel region therebetween. An insulated gate is over the first major surface and the channel regions. The plurality of spaced channel regions in each of the body regions provides the device with improved surface operating area.
摘要翻译： VDMOS器件包括具有第一和第二相对主表面的半导体材料晶片。 第一导电类型的漏极区沿着一个主表面延伸。 第二导电类型的多个体区在一个主表面处于体区。 每个体区与漏区形成体/漏PN结，其与第一主表面的交点处于闭合路径，优选为六边形。 一个导电类型的多个间隔的源极区域在每个体区域中，每个源极区域与相邻体区域中的两个源极区域之间的空间相对。 每个源区域与体区域形成源/体PN结。 源极/主体PN结中的每一个的一部分与其相应的漏极/主体PN结相邻但间隔开，以在它们之间形成沟道区。 绝缘栅极位于第一主表面和沟道区之上。 每个身体区域中的多个间隔通道区域为装置提供了改进的表面操作面积。
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公开(公告)号：US5399892A
公开(公告)日：1995-03-21
申请号：US158444
申请日：1993-11-29
IPC分类号： H01L29/06 , H01L29/739 , H01L29/78 , H01L29/10
CPC分类号： H01L29/0696 , H01L29/7802 , Y10S148/126
摘要： A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.
摘要翻译： 用于MOS门控半导体器件的晶片的图案包括从源极接触区域延伸到另一个源极接触区域的多个带，每个带子在两个沟道区域之间具有单个源极区域，以便增加器件的载流 相对于现有技术的每单位面积的能力。 该图案相对于源接触区域的面积增加了有效载流区域（器件的通道和颈部区域）的尺寸。 源极接触区可以是离散的或线性的，并且带可以从其垂直地或以其它角度延伸。
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公开(公告)号：US4639754A
公开(公告)日：1987-01-27
申请号：US705371
申请日：1985-02-25
IPC分类号： H01L21/336 , H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/78
CPC分类号： H01L29/7802 , H01L29/0696 , H01L29/1095
摘要： An IGFET device includes a semiconductor wafer having a first conductivity type drain region contiguous with a wafer surface. A second conductivity type body region extends into the wafer from the wafer surface so as to form a body/drain PN junction having an intercept at the surface; the body region further including a body-contact portion of relatively high conductivity disposed at the surface. A first conductivity type source region extends into the wafer so as to form a source/body PN junction which has first and second intercepts at the surface. The first intercept is spaced from the body/drain intercept so as to define a channel region in the body region at the surface, and the second intercept is contiguous with the body contact portion. The second intercept is relatively narrowly spaced from the first intercept along most of the length of the first intercept and is relatively widely spaced from the first intercept at one or more predetermined portions. A source electrode contacts the body-contact portion and the source region on the wafer surface.
摘要翻译： IGFET器件包括具有与晶片表面相邻的第一导电型漏极区域的半导体晶片。 第二导电类型体区域从晶片表面延伸到晶片中，以形成在表面具有截距的主体/漏极PN结; 所述主体区域还包括设置在所述表面处的相对高导电性的身体接触部分。 第一导电类型源极区域延伸到晶片中，以形成在表面具有第一和第二截距的源极/主体PN结。 第一截距与身体/排水截距间隔开，以便在表面的身体区域中限定通道区域，并且第二截距与身体接触部分相邻。 第二截距与第一截距的大部分长度上的第一截距相对较窄地间隔开，并且与一个或多个预定部分处的第一截距相比较宽。 源电极接触晶片表面上的体接触部分和源极区域。
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公开(公告)号：US4631564A
公开(公告)日：1986-12-23
申请号：US664027
申请日：1984-10-23
IPC分类号： H01L29/06 , H01L29/08 , H01L29/10 , H01L29/417 , H01L29/423 , H01L29/739 , H01L29/78
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0696 , H01L29/1095 , H01L29/7395
摘要： A VDMOS device comprises a semiconductor wafer having a major surface with a first conductivity type drain region thereat. An array of second conductivity type body regions, spaced from each other by distance D, is diffused into the drain region from the first surface. The body regions each include a relatively high conductivity supplementary body region and a first conductivity type source region diffused therein from within the first surface boundary thereof. The spacing between each source region and the drain region defines a channel region at the first surface. A source electrode contacts the source and body regions and an insulated gate electrode overlies each channel region. A gate bond pad, in direct contact with the gate electrode, overlies a second conductivity type gate shield region and is insulated therefrom. The gate shield region is contiguous with the drain region and is spaced from the neighboring channel regions by distance D. The gate shield region includes a plurality of contact areas proximate to the periphery thereof and a plurality of relatively low conductivity portions disposed between the contact areas and the drain region. The source electrode ohmically contacts these contact areas.
摘要翻译： VDMOS器件包括半导体晶片，其主表面具有第一导电型漏极区域。 通过距离D彼此间隔开的第二导电类型体区域的阵列从第一表面扩散到漏极区域。 主体区域各自包括相对高的导电性补充体区域和从其第一表面边界内扩散的第一导电型源区域。 每个源极区域和漏极区域之间的间隔限定在第一表面处的沟道区域。 源电极接触源极和主体区域，绝缘栅电极覆盖每个沟道区域。 与栅电极直接接触的栅极接合焊盘覆盖在第二导电类型的栅极屏蔽区域上并与之绝缘。 栅极屏蔽区域与漏极区域相邻并且与相邻沟道区域间隔开距离D.栅极屏蔽区域包括靠近其周边的多个接触区域和设置在接触区域之间的多个相对较低的导电部分 和漏极区域。 源电极欧姆接触这些接触区域。
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6.发明授权Method of forming MOS-gated semiconductor devices having mesh geometry pattern 失效形成具有网格几何图案的MOS门控半导体器件的方法
公开(公告)号：US5468668A
公开(公告)日：1995-11-21
申请号：US368612
申请日：1995-01-04
IPC分类号： H01L29/06 , H01L29/739 , H01L29/78 , H01L21/77
CPC分类号： H01L29/0696 , H01L29/7802 , Y10S148/126
摘要： A pattern for a wafer for a MOS-gated semiconductor device includes plural ribbons extending from a source contact region to another source contact region, each of the ribbons having a single source region between two channel regions, so as to increase the device's current-carrying capability per unit area relative to the prior art. The pattern increases the size of the active current-carrying area (the channel and neck regions of the device) relative to the area of the source contact areas. The source contact regions may be discrete or linear, and the ribbons may extend therefrom perpendicularly or at other angles.
摘要翻译： 用于MOS门控半导体器件的晶片的图案包括从源极接触区域延伸到另一个源极接触区域的多个带，每个带子在两个沟道区域之间具有单个源极区域，以便增加器件的载流 相对于现有技术的每单位面积的能力。 该图案相对于源接触区域的面积增加了有效载流区域（器件的通道和颈部区域）的尺寸。 源极接触区可以是离散的或线性的，并且带可以从其垂直地或以其它角度延伸。
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公开(公告)号：US5023692A
公开(公告)日：1991-06-11
申请号：US447330
申请日：1989-12-07
IPC分类号： H01L29/78 , H01L21/8234 , H01L27/02 , H01L27/04 , H01L27/088 , H03K17/08
CPC分类号： H01L27/0251
摘要： The present invention relates to a power MOS transistor having a current limiting circuit incorporated in the same substrate as the transistor. The power MOS transistor includes a drain region extending through the substrate between opposed first and second surfaces, a plurality of body regions in the substrate at the first surface, a separate source region in the substrate at the first surface within each body region and a channel extending across each body region between its junction with its respective source region and its junction with the drain region. A conductive gate is over and insulated from the first surface and extends over the channel regions. A first conductive electrode extends over and is insulated from the gate and contacts a first portion of the source regions. A second conductive electrode extends over and is insulated from the gate and contacts a second portion of the source regions. The second portion contains a smaller number of the source regions than the first portion. The current limiting circuit includes a bipolar transistor formed in a well region in the substrate, a zener diode formed in a second well region in the substrate and two resistors formed over and insulated from the first surface. The current limiting circuit is connected between the second portion of the source regions and the gate so as to reduce the power through the circuit.
摘要翻译： 本发明涉及一种具有与晶体管相同的衬底中的限流电路的功率MOS晶体管。 功率MOS晶体管包括在相对的第一和第二表面之间延伸穿过衬底的漏极区域，在第一表面处的衬底中的多个体区域，在每个体区域内的第一表面处的衬底中的单独源极区域和沟道 在其与其各自的源极区域的连接点及其与漏极区域的连接处的每个体区域之间延伸。 导电栅极与第一表面结合并且绝缘，并且在沟道区域上延伸。 第一导电电极延伸并且与栅极绝缘并接触源极区域的第一部分。 第二导电电极延伸并且与栅极绝缘并且接触源极区域的第二部分。 第二部分包含比第一部分少的源区域。 电流限制电路包括形成在衬底的阱区中的双极晶体管，形成在衬底中的第二阱区中的齐纳二极管和形成在第一表面上并与第一表面绝缘的两个电阻。 电流限制电路连接在源区的第二部分和栅极之间，以便减小通过电路的功率。
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公开(公告)号：US4532534A
公开(公告)日：1985-07-30
申请号：US415486
申请日：1982-09-07
CPC分类号： H01L29/7811 , H01L29/0696 , H01L29/0865 , H01L29/1095 , H01L29/402
摘要： A vertical MOSFET device includes a major surface having an active, gate-controlled portion adjacent to an inactive portion. A gate-controlled perimeter channel is disposed at the boundary between the active and inactive portions.
摘要翻译： 垂直MOSFET器件包括具有与非活性部分相邻的有源栅极控制部分的主表面。 门控周边通道设置在有效部分和非活动部分之间的边界处。
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公开(公告)号：US4260946A
公开(公告)日：1981-04-07
申请号：US22840
申请日：1979-03-22
摘要： A temperature-independent reference voltage is developed as the difference between the offset potentials across first and second diode means, the second nested within the first to conduct the same forward bias current.
摘要翻译： 开发独立于温度的参考电压作为跨越第一和第二二极管装置的偏置电位之间的差异，第二嵌套在第一和第二二极管装置之间以进行相同的正向偏置电流。
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10.发明授权
公开(公告)号：US4677324A
公开(公告)日：1987-06-30
申请号：US842651
申请日：1986-03-21
IPC分类号： H03K17/04 , H03K17/56 , H03K17/567 , H03K17/687 , H03K3/33 , H03K3/353
CPC分类号： H03K17/567 , H03K17/0406
摘要： A fast switch-off circuit for a conductivity modulated field effect transistor (COMFET) avoids the flow of destructive latch-up currents. A reduced-amplitude switch-off current is applied to the gate electrode of the COMFET during the initial portion of switch-off. When the source-to-drain voltage (V.sub.DS) of the COMFET has become larger than the range of low V.sub.DS voltage in which latch-up can occur for an increased-amplitude switch-off current being applied to the gate electrode of the COMFET, that increased-amplitude switch-off current is applied to the gate electrode of the COMFET.
摘要翻译： 用于导电性调制场效应晶体管（COMFET）的快速关断电路避免了破坏性闭锁电流的流动。 在关断的初始部分，向COMFET的栅电极施加减小幅度的关断电流。 当COMFET的源极至漏极电压（VDS）已经变得大于施加到COMFET的栅电极的增加幅度的关断电流时可能发生闩锁的低VDS电压的范围， 该增加幅度的关断电流被施加到COMFET的栅电极。
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