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23 条记录 (耗时 0.033 秒)

    Sub-critical-dimension integrated circuit features
    3.
    发明授权
    Sub-critical-dimension integrated circuit features 有权

    公开(公告)号：US06686300B2

    公开(公告)日：2004-02-03

    申请号：US10055262

    申请日：2001-10-25

    申请人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

    发明人： Manoj Mehrotra ,  John N. Randall ,  Mark S. Rodder

    IPC分类号： H01L21302

    CPC分类号： H01L29/4238 ,  H01L21/28123 ,  H01L21/32139 ,  H01L29/1033 ,  Y10S438/945

    摘要： A method of photolithographically forming an integrated circuit feature, such as a conductive structure, for example a gate electrode (15), or such as a patterned insulator feature, is disclosed. A critical dimension (CD) for a photolithography process defines a minimum line width of photoresist or other masking material that may be patterned by the process. A photomask (20, 30, 40, 50, 60) has a mask feature (25, 35, 45, 55, 65) that has varying width portions along its length. The wider portions have a width (L1) that is at or above the critical dimension of the process, while the narrower portions have a width (L2) that is below the critical dimension of the process. In the case of a patterned etch of a conductor, photoexposure and etching of conductive material using the photomask (20, 30, 40, 50, 60) defines a gate electrode (15) for a transistor (10) that has a higher drive current than a transistor having a uniform gate width at the critical dimension.

    Optical proximity correction
    4.
    发明授权
    Optical proximity correction 有权
    光学邻近校正

    公开(公告)号：US06634018B2

    公开(公告)日：2003-10-14

    申请号：US09935452

    申请日：2001-08-23

    申请人： John N. Randall ,  Thomas J. Aton ,  Shane R. Palmer

    发明人： John N. Randall ,  Thomas J. Aton ,  Shane R. Palmer

    IPC分类号： G06F1750

    CPC分类号： G03F1/36 ,  G03F7/70441

    摘要： An improvement to the optical proximity correction process used in photolithography. Mask pattern modeling is added to the optical proximity correction process, producing patterns that are optimized for both reticle manufacture and wafer fabrication. Pattern validation is improved by applying a mask pattern model and a wafer pattern model to the validation process. Reticle inspection is improved by adding a mask inspection tool model that comprehends the limitations of the inspection tool.

    摘要翻译： 对光刻中使用的光学邻近校正处理的改进。 将掩模图案建模添加到光学邻近校正过程中，产生针对标线制造和晶片制造而优化的图案。 通过将掩模图案模型和晶片图案模型应用于验证过程来改进图案验证。 通过添加一个了解检测工具限制的面罩检查工具模型，可以改进掩模检查。

    Method of forming a low distortion stencil mask
    5.
    发明授权
    Method of forming a low distortion stencil mask 失效
    形成低失真模板掩模的方法

    公开(公告)号：US5529862A

    公开(公告)日：1996-06-25

    申请号：US115954

    申请日：1993-09-01

    申请人： John N. Randall

    发明人： John N. Randall

    IPC分类号： G03F1/20 ,  G03F9/00

    CPC分类号： G03F1/20

    摘要： A stencil mask (10) has a membrane (14) under tensile stress and at least one pattern opening (22) formed through the membrane (14). A plurality of stress relief openings (30) are formed in the membrane for reducing stress-induced distortion of the membrane and the mask pattern. The stress relief openings (30) are positioned to relieve concentrations of stress within the membrane (14) such as those resulting from non-regularities within the pattern. In one embodiment, a screening material (56), less rigid than the membrane (14), is contained within the stress relief openings (30). Methods of forming such masks (10) are also disclosed.

    摘要翻译： 模板掩模（10）具有在拉伸应力下的膜（14）和穿过膜（14）形成的至少一个图案开口（22）。 在膜中形成多个应力消除开口（30），用于减少膜的应力诱导变形和掩模图案。 应力释放开口（30）被定位成减轻膜（14）内的应力的浓度，例如由图案内的非规则产生的应力的浓度。 在一个实施例中，在应力释放开口（30）内容纳有比膜（14）刚性低的筛选材料（56）。 还公开了形成这种掩模（10）的方法。

    Integrated circuit layout and verification method
    6.
    发明授权
    Integrated circuit layout and verification method 有权

    公开(公告)号：US06553558B2

    公开(公告)日：2003-04-22

    申请号：US09737680

    申请日：2000-12-14

    申请人： Shane R. Palmer ,  John N. Randall ,  Thomas J. Aton

    发明人： Shane R. Palmer ,  John N. Randall ,  Thomas J. Aton

    IPC分类号： G06F1750

    CPC分类号： G03F1/36 ,  G03F7/70441

    摘要： A method of performing and verifying an integrated circuit layout is provided that comprises the steps of performing the layout of a mask. Proximity correction techniques are then applied to the mask layout data. Theoretical contours which comprise curvilinear forms are then extrapolated from the corrected mask data set. The curvilinear contour data is then bounded using boxing algorithms in order to generate a bounded contour data set. The bounded contour data set can then be compared to the original input mask data to detect design rule violations and other characteristics of the original layout.

    Stretching device
    7.
    发明授权
    Stretching device 失效
    拉伸装置

    公开(公告)号：US5335649A

    公开(公告)日：1994-08-09

    申请号：US637921

    申请日：1991-01-07

    申请人： John N. Randall ,  James R. Wooley ,  William H. Fagan

    发明人： John N. Randall ,  James R. Wooley ,  William H. Fagan

    IPC分类号： A61H1/02

    CPC分类号： A61H1/02 ,  A61H1/024 ,  A61H1/0244 ,  A61H1/0274 ,  A61H1/0281 ,  A61H2001/0203 ,  A61H2203/0431

    摘要： A proprioceptive neuromuscular facilitation exercise device including a drive motor, gear mechanism connected with the drive motor, a control connected with the motor for operating the motor in either direction, and a rotating member connected with the gear mechanism and adapted to be coupled to a body member of a user for moving the body member in the desired direction. The movable member moves in increments and is lockable at desired positions for holding the body member against a force tending to return it to normal position or a force in the opposite direction. One exercise device rotates the upper torso relative to the spine. Another of the exercise devices rotates the upper legs of a user relative to the hip joints and lower legs relative to the knees. A further device operates the arms forward and backward relative to the shoulder joint and includes parallel vertical shafts movable together and apart to adjust for difference distances between the shoulder joints of a user.

    摘要翻译： 本发明的神经肌肉促进运动装置，包括驱动马达，与驱动马达连接的齿轮机构，与马达连接的用于在任一方向上操作马达的控制器，以及与齿轮机构连接并适于联接到主体的旋转部件 用户的构件，用于沿所需方向移动身体构件。 可移动构件以增量移动并且可锁定在期望的位置处，用于保持身体构件抵抗趋向于将其返回到正常位置的力或在相反方向上的力。 一个运动装置相对于脊柱旋转上身。 另一个锻炼装置相对于膝盖相对于髋关节和小腿旋转使用者的上腿。 另一装置相对于肩关节向前和向后操作臂，并且包括可一起移动并分开的平行垂直轴，以调节用户的肩关节之间的差距。

    Method of forming a quantum effect switching device
    8.
    发明授权
    Method of forming a quantum effect switching device 失效
    形成量子效应开关器件的方法

    公开(公告)号：US5096846A

    公开(公告)日：1992-03-17

    申请号：US608406

    申请日：1990-11-02

    申请人： John N. Randall

    发明人： John N. Randall

    IPC分类号： H01L21/28 ,  H01L21/308 ,  H01L21/335

    CPC分类号： B82Y10/00 ,  H01L21/28 ,  H01L21/3085 ,  H01L29/66469 ,  Y10S148/10 ,  Y10S438/962

    摘要： A method for forming a quantum effect switching device is disclosed which comprises the step of forming a heterostructure substrate 10. A silicon nitride layer 22 is formed on an outer surface of the substrate 10. An aluminum mask body 30 is formed using a lift-off procedure. Aluminum mask body 30 is then used to form a silicon nitride mask body 32 from the silicon nitride layer 22 using a CF.sub.4 /O.sub.2 reactive ion etch process. A boron trichloride etch process is then used to form a dual column structure 34 while removing the aluminum mask body 30. A buffered HF wet etch process removes the silicon nitride mask body 32. Separate metal contacts can then be made to electrically separate points on the outer surface of the dual column structure 34.

    摘要翻译： 公开了一种用于形成量子效应开关器件的方法，其包括形成异质结构衬底10的步骤。在衬底10的外表面上形成氮化硅层22.铝掩模体30使用剥离 程序。 然后使用铝掩模体30，使用CF4 / O2反应离子蚀刻工艺从氮化硅层22形成氮化硅掩模体32。 然后在去除铝掩模体30的同时，使用三氯化硼蚀刻工艺来形成双重柱结构34.缓冲的HF湿法蚀刻工艺去除氮化硅掩模体32.然后可以将独立的金属接触件电分离在 双柱结构34的外表面。

    Method for designing matrix paintings and determination of paint distribution
    9.
    发明授权
    Method for designing matrix paintings and determination of paint distribution 失效
    矩阵绘画设计方法和油漆分布测定

    公开(公告)号：US06813378B2

    公开(公告)日：2004-11-02

    申请号：US09838588

    申请日：2001-04-18

    申请人： John N. Randall ,  Christian H. Seidler

    发明人： John N. Randall ,  Christian H. Seidler

    IPC分类号： G06K936

    CPC分类号： G06T11/001

    摘要： A design tool which accepts the input of a grayscale underpainting and a number of artistic selections, such as primary colors, levels of intensity for each color, and lines of color drawn on a copy of the grayscale underpainting and forms a data base which can be used by a painting tool to create a Matrix painting.

    摘要翻译： 一种设计工具，其接受灰度不足印象的输入和多种艺术选择，例如原色，每种颜色的强度级别，以及在灰度不足印画的副本上绘制的颜色线，并形成数据库，其可以是 由绘画工具用来创建一个矩阵绘画。

    Universal quantum dot logic cell
    10.
    发明授权
    Universal quantum dot logic cell 失效
    通用量子点逻辑单元

    公开(公告)号：US5783840A

    公开(公告)日：1998-07-21

    申请号：US472108

    申请日：1995-06-07

    申请人： John N. Randall ,  Gary A. Frazier

    发明人： John N. Randall ,  Gary A. Frazier

    IPC分类号： H01L29/68 ,  H01L27/06 ,  H01L29/06 ,  H01L29/66 ,  H01L29/772 ,  H03K19/02

    CPC分类号： B82Y10/00 ,  H01L27/0605 ,  H01L29/772 ,  Y10S148/016

    摘要： A quantum dot logic unit (8) is provided which comprises a row of quantum dots (14, 16, and 18), with each quantum dot separated by vertical heterojunction tunneling barriers (20, 22, 24, and 26). Electric potentials placed on inputs (32, 34, and 36) are operable to modulate quantum states within the quantum dots, thus controlling electron tunneling through the tunneling barriers.

    摘要翻译： 提供量子点逻辑单元（8），其包括一行量子点（14,16和18），每个量子点由垂直异质结隧道势垒（20,22,24和26）分隔开。 放置在输入端（32,34和36）上的电位可用于调制量子点内的量子态，从而控制通过隧道势垒的电子隧穿。