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    Non-volatile memory with source-side column select
    1.
    发明授权
    Non-volatile memory with source-side column select 有权
    源极列选择非易失性存储器

    公开(公告)号：US07522453B1

    公开(公告)日：2009-04-21

    申请号：US11961134

    申请日：2007-12-20

    申请人： Zhigang Wang ,  Gregory Bakker ,  Volker Hecht ,  Santosh Yachareni ,  Fethi Dhaoui ,  Vidyadhara Bellippady

    发明人： Zhigang Wang ,  Gregory Bakker ,  Volker Hecht ,  Santosh Yachareni ,  Fethi Dhaoui ,  Vidyadhara Bellippady

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0416 ,  G11C16/08

    摘要： A non-volatile memory array segment includes an odd-select transistor having a drain coupled to an odd-source line and an even-select transistor having a drain coupled to an even-source line. Two segment-select transistors have drains coupled to the sources of different ones of the odd and even source lines, sources coupled to ground, and gates coupled to a segment-select line. A plurality of odd non-volatile memory transistors each has a drain coupled to a common drain line, a source coupled to the odd-source line, a floating gate, and a control gate. A plurality of even non-volatile memory transistors, each has a drain coupled to the common drain line, a source coupled to the even-source line, a floating gate, and a control gate. The control gate of each even non-volatile memory transistor is coupled to the control gate of a different one of the odd non-volatile memory transistors.

    摘要翻译： 非易失性存储器阵列段包括具有耦合到奇数源极线的漏极和耦合到偶数源极线的漏极的偶数选择晶体管的奇数选择晶体管。 两个段选择晶体管具有耦合到奇数和偶数源极线的不同源极，耦合到地的源极和耦合到段选择线的栅极的漏极。 多个奇数非易失性存储晶体管各自具有耦合到公共漏极线的漏极，耦合到奇数源极线的源极，浮动栅极和控制栅极。 多个偶数非易失性存储晶体管每个都具有耦合到公共漏极线的漏极，耦合到偶数源极线的源极，浮动栅极和控制栅极。 每个偶数非易失性存储晶体管的控制栅极耦合到奇数非易失性存储晶体管中不同一个的控制栅极。

    PLD PROVIDING SOFT WAKEUP LOGIC
    2.
    发明申请
    PLD PROVIDING SOFT WAKEUP LOGIC 有权
    PLD提供软件唤醒逻辑

    公开(公告)号：US20100156457A1

    公开(公告)日：2010-06-24

    申请号：US12340358

    申请日：2008-12-19

    申请人： Jonathan W. Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    发明人： Jonathan W. Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    IPC分类号： H03K19/177 ,  H03K19/0175

    CPC分类号： H03K19/17784

    摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

    摘要翻译： 公开了具有多个可编程区域的可编程逻辑器件（PLD）。 一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。 在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

    PLD providing soft wakeup logic
    3.
    发明授权
    PLD providing soft wakeup logic 有权
    PLD提供软唤醒逻辑

    公开(公告)号：US07884640B2

    公开(公告)日：2011-02-08

    申请号：US12340358

    申请日：2008-12-19

    申请人： Jonathan W Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    发明人： Jonathan W Greene ,  Gregory Bakker ,  Vidyadhara Bellippady ,  Volker Hecht ,  Theodore Speers

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17784

    摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.

    摘要翻译： 公开了具有多个可编程区域的可编程逻辑器件（PLD）。 一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。 在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。

    Error-detecting and correcting FPGA architecture
    4.
    发明授权
    Error-detecting and correcting FPGA architecture 有权
    错误检测和校正FPGA架构

    公开(公告)号：US07937647B2

    公开(公告)日：2011-05-03

    申请号：US11829335

    申请日：2007-07-27

    申请人： Vidyadhara Bellipaddy ,  Gregory Bakker

    发明人： Vidyadhara Bellipaddy ,  Gregory Bakker

    IPC分类号： G11C29/00 ,  H03M13/00

    CPC分类号： H03K19/1776 ,  G06F11/1052 ,  G11C2029/0411 ,  H03K19/17764

    摘要： A method and apparatus are provided for an error-correcting FPGA. ECC data for configuration is generated and programmed into the ECC rows in the configuration memory. While booting, it is determined whether an integrity-check bit is set. If so, an integrity check is performed. If a single-bit error is detected, if the bit error is an erroneous “0” value, the memory location containing the erroneous “0” value is reprogrammed to a “1” value. If the bit error is an erroneous “1,” value, the memory block data is saved in a non-volatile memory block, the configuration memory block containing the error is erased and reprogrammed using the corrected bit. If there is more than one error, an error flag is set. The user reads the status of the error flag through the JTAG port. If the error flag is set then a full reprogramming cycle is initiated.

    摘要翻译： 提供了用于纠错FPGA的方法和装置。 生成用于配置的ECC数据并将其编程到配置存储器中的ECC行中。 在引导时，确定是否设置完整性校验位。 如果是这样，则执行完整性检查。 如果检测到单位错误，如果位错误是错误的“0”值，则包含错误“0”值的存储器位置被重新编程为“1”值。 如果位错误是错误的“1”值，则存储器块数据被保存在非易失性存储器块中，包含该错误的配置存储器块被擦除并且使用校正位被重新编程。 如果存在多个错误，则设置错误标志。 用户通过JTAG端口读取错误标志的状态。 如果设置了错误标志，则启动完整的重新编程周期。

    Power-up and power-down circuit for system-on-a-chip integrated circuit
    5.
    发明授权
    Power-up and power-down circuit for system-on-a-chip integrated circuit 有权
    用于片上系统集成电路的上电和掉电电路

    公开(公告)号：US07911226B2

    公开(公告)日：2011-03-22

    申请号：US11467279

    申请日：2006-08-25

    申请人： Gregory Bakker

    发明人： Gregory Bakker

    IPC分类号： H03K19/173 ,  G05F1/00 ,  G05F5/00

    CPC分类号： G11C5/147 ,  H01L2924/0002 ,  H03K17/22 ,  Y10T307/50 ,  Y10T307/724 ,  H01L2924/00

    摘要： A power-up and power-down circuit for an integrated circuit includes a voltage regulator set for a first voltage. A first I/O pad is coupled internally to an input to the voltage regulator and to first internal circuits. The second voltage is externally coupled to the first I/O pad. A second I/O pad is coupled internally to an output of the voltage regulator configured to drive the base of an external transistor. A third I/O pad of the integrated circuit is coupled internally to a reference-voltage input of the voltage regulator. A fourth I/O pad is coupled to a feedback input of the voltage regulator. A fifth I/O pad of the integrated circuit is coupled internally to logic circuitry that controls power-up and power down of the integrated circuit from internal signals including internal signals from a real-time clock circuit disposed on the integrated circuit.

    摘要翻译： 用于集成电路的上电和掉电电路包括用于第一电压的电压调节器。 第一个I / O焊盘内部耦合到电压调节器和第一个内部电路的输入端。 第二电压外部耦合到第一I / O焊盘。 第二I / O焊盘内部耦合到被配置为驱动外部晶体管的基极的电压调节器的输出端。 集成电路的第三个I / O焊盘内部耦合到电压调节器的参考电压输入端。 第四I / O焊盘耦合到电压调节器的反馈输入端。 集成电路的第五个I / O焊盘内部耦合到逻辑电路，该逻辑电路从包括设置在集成电路上的实时时钟电路的内部信号的内部信号控制集成电路的上电和掉电。

    Programmable logic device with a microcontroller-based control system
    6.
    发明授权
    Programmable logic device with a microcontroller-based control system 有权
    可编程逻辑器件，具有基于微控制器的控制系统

    公开(公告)号：US07683660B1

    公开(公告)日：2010-03-23

    申请号：US12023299

    申请日：2008-01-31

    申请人： Gregory Bakker ,  Joel Landry ,  William C. Plants

    发明人： Gregory Bakker ,  Joel Landry ,  William C. Plants

    IPC分类号： H03K19/173

    CPC分类号： H03K19/1733 ,  G06F17/5054

    摘要： A computer program product in a computer-readable medium for use in a microcontroller-based control system in a programmable logic integrated circuit device is disclosed. The computer program product comprises first instructions for initializing the device, second instructions for reading programming data from a data source external to the programmable logic integrated circuit device, third instructions for transferring the programming data into control elements internal to the programmable logic integrated circuit device. Provision is made for fourth instructions for saving at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device into a non-volatile memory block and for fifth instructions for restoring at least a part of the internal logic state of the user logic programmed into the programmable logic integrated circuit device from a non-volatile memory block. The programmable logic integrated circuit device, comprises a microcontroller block and a programmable logic block with programming circuitry, and has a sub-bus which couples the microcontroller block to the programming circuitry.

    摘要翻译： 公开了一种用于可编程逻辑集成电路装置中基于微控制器的控制系统的计算机可读介质中的计算机程序产品。 计算机程序产品包括用于初始化设备的第一指令，用于从可编程逻辑集成电路器件外部的数据源读取编程数据的第二指令，用于将编程数据传送到可编程逻辑集成电路器件内部的控制元件的第三指令。 规定了第四条指令，用于将编程到可编程逻辑集成电路设备中的用户逻辑的内部逻辑状态的至少一部分保存到非易失性存储器块中，以及用于恢复内部逻辑的至少一部分的第五指令 从非易失性存储器块编程到可编程逻辑集成电路器件中的用户逻辑状态。 可编程逻辑集成电路器件包括微控制器模块和具有编程电路的可编程逻辑模块，并且具有将微控制器模块耦合到编程电路的子总线。

    VOLTAGE- AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT
    10.
    发明申请
    VOLTAGE- AND TEMPERATURE-COMPENSATED RC OSCILLATOR CIRCUIT 审中-公开
    电压和温度补偿RC振荡器电路

    公开(公告)号：US20080284532A1

    公开(公告)日：2008-11-20

    申请号：US12182329

    申请日：2008-07-30

    申请人： Gregory Bakker

    发明人： Gregory Bakker

    IPC分类号： H03K3/26 ,  H03K3/02 ,  H03K3/42 ,  H03L1/00

    CPC分类号： H03K3/0231 ,  H03K3/011 ,  H03L1/022

    摘要： An integrated temperature-compensated RC oscillator circuit includes an inverter having an input and an output. An RC network is coupled between the inverter and a pair of comparators. A first comparator has an inverting input coupled to a first reference voltage, a non-inverting input coupled to the RC network, and an output. A second comparator has an inverting input coupled to the RC network, a non-inverting input coupled to a second reference voltage, and an output. A set-reset flip-flop has a set input coupled to the output of the first comparator, a reset input coupled to the output of the second comparator, and an output coupled to the input of the inverter. Differential amplifiers in the comparators each have a diode-connected p-channel MOS transistor controlling a mirrored p-channel MOS transistor whose channel width is less than that of the diode-connected p-channel current mirror transistor.

    摘要翻译： 集成温度补偿RC振荡器电路包括具有输入和输出的反相器。 RC网络耦合在逆变器和一对比较器之间。 第一比较器具有耦合到第一参考电压的反相输入，耦合到RC网络的非反相输入和输出。 第二比较器具有耦合到RC网络的反相输入，耦合到第二参考电压的非反相输入和输出。 设置复位触发器具有耦合到第一比较器的输出的设置输入，耦合到第二比较器的输出的复位输入和耦合到反相器的输入的输出。 比较器中的差分放大器各自具有二极管连接的p沟道MOS晶体管，其控制沟道宽度小于二极管连接的p沟道电流镜晶体管的p沟道MOS晶体管。