公开(公告)号：US20070236863A1

公开(公告)日：2007-10-11

申请号：US11486065

申请日：2006-07-14

申请人： Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Jae-hyoung Choi

发明人： Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Kyoung-ryul Yoon ,  Ki-vin Im ,  Jae-hyoung Choi

IPC分类号： H01G4/06 ,  H01G7/00

CPC分类号： H01G4/10 ,  H01G4/33 ,  Y10T29/435

摘要： A capacitor may have a pre-treatment layer formed on a lower electrode, reaction to a dielectric layer and/or deterioration of capacitor characteristics may be suppressed. At least part of the dielectric layer may be oxidized or nitridized after being oxidized, and increases in leakage current may be suppressed. In a method of fabricating a capacitor, a plasma treatment performed before and after the forming of the dielectric layer within the batch-type equipment may cause retention time between the plasma treatment and the deposition of the dielectric layer to be the same or substantially the same for each wafer and/or capacitors may show smaller variations in layer characteristics between wafers.

摘要翻译： 电容器可以具有形成在下电极上的预处理层，对电介质层的反应和/或电容器特性的劣化被抑制。 电介质层的至少一部分可以在被氧化后被氧化或氮化，并且可以抑制漏电流的增加。 在制造电容器的方法中，在分批式设备中形成电介质层之前和之后执行的等离子体处理可能导致等离子体处理和介电层沉积之间的保持时间相同或基本相同 对于每个晶片和/或电容器可以在晶片之间的层特性中显示较小的变化。

公开(公告)号：US07422943B2

公开(公告)日：2008-09-09

申请号：US11386660

申请日：2006-03-22

申请人： Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Jae-hyoung Choi ,  Se-hoon Oh ,  Hong-bum Park

发明人： Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Jae-hyoung Choi ,  Se-hoon Oh ,  Hong-bum Park

IPC分类号： H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/75

摘要： Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.

摘要翻译： 提供具有包括下电极，电介质层和包括导电金属氮化物层和掺杂多晶硅锗层的上电极的上电极的电容器。 导电金属氮化物层的至少一部分被氧化和/或至少部分介电层被氮化。

公开(公告)号：US20070040203A1

公开(公告)日：2007-02-22

申请号：US11386660

申请日：2006-03-22

申请人： Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Jae-hyoung Choi ,  Se-hoon Oh ,  Hong-bum Park

发明人： Jong-cheol Lee ,  Young-sun Kim ,  Jung-hee Chung ,  Jae-hyoung Choi ,  Se-hoon Oh ,  Hong-bum Park

IPC分类号： H01L27/108

CPC分类号： H01L28/91 ,  H01L27/10817 ,  H01L27/10852 ,  H01L28/75

摘要： Capacitors having upper electrodes that include a lower electrode, a dielectric layer and an upper electrode that includes a conductive metal nitride layer and a doped polysilicon germanium layer are provided. At least part of the conductive metal nitride layer is oxidized and/or at least part of the dielectric layer is nitridized.

摘要翻译： 提供具有包括下电极，电介质层和包括导电金属氮化物层和掺杂多晶硅锗层的上电极的上电极的电容器。 导电金属氮化物层的至少一部分被氧化和/或至少部分介电层被氮化。

公开(公告)号：US07824501B2

公开(公告)日：2010-11-02

申请号：US11781334

申请日：2007-07-23

申请人： Hoon-sang Choi ,  Jong-cheol Lee ,  Ki-vin Im ,  Eun-ae Chung ,  Sang-yeol Kang ,  Young-sun Kim ,  Kwang-hee Lee

发明人： Hoon-sang Choi ,  Jong-cheol Lee ,  Ki-vin Im ,  Eun-ae Chung ,  Sang-yeol Kang ,  Young-sun Kim ,  Kwang-hee Lee

IPC分类号： B08B9/08 ,  B08B3/08 ,  B08B3/10 ,  B08B5/00

CPC分类号： C23C16/45525 ,  C23C16/4401 ,  C23C16/45544

摘要： Provided is an in-situ method of cleaning a vaporizer of an atomic layer deposition apparatus during a dielectric layer deposition process, to prevent nozzle blocking in the vaporizer and an atomic layer deposition apparatus. During the dielectric layer deposition process, the following steps are repeated: supplying a first source gas for dielectric layer deposition into a chamber of an atomic layer deposition apparatus; purging the first source gas; supplying a second source gas into the chamber of the atomic layer deposition apparatus; purging the second source gas, the in-situ method of cleaning the vaporizer is performed after supplying the first source gas for dielectric layer deposition and before supplying the first source gas again.

摘要翻译： 提供了一种在电介质层沉积工艺期间清洁原子层沉积设备的蒸发器的原位方法，以防止蒸发器和原子层沉积设备中的喷嘴堵塞。 在电介质层沉积过程中，重复以下步骤：将用于电介质层沉积的第一源气体供应到原子层沉积设备的腔室中; 净化第一源气; 将第二源气体供应到原子层沉积设备的腔室中; 吹扫第二源气体时，在供给用于电介质层沉积的第一源气体并再次供应第一源气体之前执行清洗蒸发器的原位方法。

公开(公告)号：US20080121184A1

公开(公告)日：2008-05-29

申请号：US11781334

申请日：2007-07-23

申请人： Hoon-sang Choi ,  Jong-cheol Lee ,  Ki-vin Im ,  Eun-ae Chung ,  Sang-yeol Kang ,  Young-sun Kim ,  Kwang-hee Lee

发明人： Hoon-sang Choi ,  Jong-cheol Lee ,  Ki-vin Im ,  Eun-ae Chung ,  Sang-yeol Kang ,  Young-sun Kim ,  Kwang-hee Lee

IPC分类号： B08B5/00 ,  C23C16/00

CPC分类号： C23C16/45525 ,  C23C16/4401 ,  C23C16/45544

摘要： Provided is an in-situ method of cleaning a vaporizer of an atomic layer deposition apparatus during a dielectric layer deposition process, to prevent nozzle blocking in the vaporizer and an atomic layer deposition apparatus. During the dielectric layer deposition process, the following steps are repeated: supplying a first source gas for dielectric layer deposition into a chamber of an atomic layer deposition apparatus; purging the first source gas; supplying a second source gas into the chamber of the atomic layer deposition apparatus; purging the second source gas, the in-situ method of cleaning the vaporizer is performed after supplying the first source gas for dielectric layer deposition and before supplying the first source gas again.

摘要翻译： 提供了一种在电介质层沉积工艺期间清洁原子层沉积设备的蒸发器的原位方法，以防止蒸发器和原子层沉积设备中的喷嘴堵塞。 在电介质层沉积过程中，重复以下步骤：将用于电介质层沉积的第一源气体供应到原子层沉积设备的腔室中; 净化第一源气; 将第二源气体供应到原子层沉积设备的腔室中; 吹扫第二源气体时，在供给用于电介质层沉积的第一源气体并再次供应第一源气体之前执行清洗蒸发器的原位方法。

公开(公告)号：US07973352B2

公开(公告)日：2011-07-05

申请号：US12754713

申请日：2010-04-06

申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

IPC分类号： H01L29/94

CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

公开(公告)号：US07723770B2

公开(公告)日：2010-05-25

申请号：US11210332

申请日：2005-08-24

申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

IPC分类号： H01L27/108

CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

公开(公告)号：US20100117194A1

公开(公告)日：2010-05-13

申请号：US12639184

申请日：2009-12-16

申请人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

发明人： Eun-ae Chung ,  Jae-hyoung Choi ,  Jung-hee Chung ,  Young-sun Kim ,  Cha-young Yoo

IPC分类号： H01L29/92 ,  H01G4/06 ,  H01G4/008

CPC分类号： H01L21/7687 ,  H01L27/10852 ,  H01L28/65 ,  H01L28/75

摘要： A metal-insulator-metal (MIM) capacitor includes a lower electrode, a dielectric layer, and an upper electrode. The lower electrode includes a first conductive layer, a chemical barrier layer on the first conductive layer, and a second conductive layer on the chemical barrier layer. The chemical barrier layer is between the first and second conductive layers and is a different material than the first and second conductive layers. The dielectric layer is on the lower electrode. The upper electrode is on the dielectric layer opposite to the lower electrode. The first and second conductive layers can have the same thickness. The chemical barrier layer can be thinner than each of the first and second conductive layers. Related methods are discussed.

摘要翻译： 金属绝缘体金属（MIM）电容器包括下电极，电介质层和上电极。 下电极包括第一导电层，第一导电层上的化学阻挡层和化学阻挡层上的第二导电层。 化学屏障层位于第一和第二导电层之间，并且是与第一和第二导电层不同的材料。 介电层位于下电极上。 上电极位于与下电极相对的电介质层上。 第一和第二导电层可以具有相同的厚度。 化学阻挡层可以比第一和第二导电层中的每一个薄。 讨论相关方法。

公开(公告)号：US08344439B2

公开(公告)日：2013-01-01

申请号：US13171163

申请日：2011-06-28

申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

IPC分类号： H01L29/94

CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。

公开(公告)号：US20100187655A1

公开(公告)日：2010-07-29

申请号：US12754713

申请日：2010-04-06

申请人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

发明人： Jae-hyoung Choi ,  Jung-hee Chung ,  Cha-young Yoo ,  Young-sun Kim ,  Se-hoon Oh

IPC分类号： H01L29/92

CPC分类号： H01L29/92 ,  H01L27/10852 ,  H01L28/40

摘要： Integrated circuit capacitors have composite dielectric layers therein. These composite dielectric layers include crystallization inhibiting regions that operate to increase the overall crystallization temperature of the composite dielectric layer. An integrated circuit capacitor includes first and second capacitor electrodes and a capacitor dielectric layer extending between the first and second capacitor electrodes. The capacitor dielectric layer includes a composite of a first dielectric layer extending adjacent the first capacitor electrode, a second dielectric layer extending adjacent the second capacitor electrode and an electrically insulating crystallization inhibiting layer extending between the first and second dielectric layers. The electrically insulating crystallization inhibiting layer is formed of a material having a higher crystallization temperature characteristic relative to the first and second dielectric layers.

摘要翻译： 集成电路电容器在其中具有复合电介质层。 这些复合电介质层包括用于增加复合介电层的整体结晶温度的结晶抑制区。 集成电路电容器包括第一和第二电容器电极和在第一和第二电容器电极之间延伸的电容器介电层。 电容器介电层包括邻近第一电容器电极延伸的第一电介质层，邻近第二电容器电极延伸的第二电介质层和在第一和第二电介质层之间延伸的电绝缘的结晶抑制层的复合材料。 电绝缘结晶抑制层由相对于第一和第二介电层具有较高结晶温度特性的材料形成。