Methods for forming metal interconnections for semiconductor devices having multiple metal depositions
    1.
    发明授权
    Methods for forming metal interconnections for semiconductor devices having multiple metal depositions 有权
    用于形成具有多个金属沉积的半导体器件的金属互连的方法

    公开(公告)号:US06964922B2

    公开(公告)日:2005-11-15

    申请号:US10353386

    申请日:2003-01-28

    摘要: Methods of forming an integrated circuit device can include forming an interlevel dielectric film on an integrated circuit substrate including a conductive portion thereof. The interlevel dielectric film includes a contact hole therein exposing a portion of the conductive portion of the integrated circuit substrate, and the dielectric film includes a trench therein communicating with the contact hole wherein the trench is in a surface of the interlevel dielectric film opposite the integrated circuit substrate. A first metal layer is formed in the contact hole preferentially with respect to formation of the first metal layer on a surface of the interlevel dielectric film opposite the integrated circuit substrate. After preferentially forming the first metal layer in the contact hole, a second metal layer is formed on the surface of the interlevel dielectric film opposite the integrated circuit substrate.

    摘要翻译: 形成集成电路器件的方法可以包括在包括其导电部分的集成电路衬底上形成层间电介质膜。 所述层间电介质膜包括露出所述集成电路基板的所述导电部分的一部分的接触孔,并且所述电介质膜包括与所述接触孔连通的沟槽,其中所述沟槽位于所述层间绝缘膜的与所述集成电路基板相对的表面中 电路基板。 相对于与集成电路基板相对的层间电介质膜的表面,优选在接触孔中形成第一金属层以形成第一金属层。 在接触孔中优先形成第一金属层之后,在与集成电路基板相对的层间绝缘膜的表面上形成第二金属层。

    Semiconductor devices having multilevel interconnections and methods for manufacturing the same
    2.
    发明授权
    Semiconductor devices having multilevel interconnections and methods for manufacturing the same 有权
    具有多层互连的半导体器件及其制造方法

    公开(公告)号:US06747354B2

    公开(公告)日:2004-06-08

    申请号:US10370222

    申请日:2003-02-19

    IPC分类号: H01L2348

    摘要: A semiconductor device includes a first metal interconnection layer on a semiconductor substrate, an intermetal dielectric layer on the first metal interconnection layer and a second metal interconnection layer formed on the intermetal dielectric layer. A contact stud electrically connects the first and second metal interconnection layers through the intermetal dielectric layer, and includes a titanium/aluminum (TiAlx) core extending from the first metal interconnection layer toward the second metal interconnection layer. In method embodiments, a portion of an insulating layer of a semiconductor substrate is removed to form a hole that exposes an underlying conductive layer. A glue layer, e.g., a titanium (Ti) layer, is formed on bottom and sidewalls of the hole. A Ti seed layer is formed on the glue layer in the hole. An aluminum-containing layer is formed on the Ti seed layer. The substrate is thermally treated to form a contact stud including a TiAlx core.

    摘要翻译: 半导体器件包括在半导体衬底上的第一金属互连层,第一金属互连层上的金属间电介质层和形成在金属间电介质层上的第二金属互连层。 接触柱将第一和第二金属互连层通过金属间电介质层电连接,并且包括从第一金属互连层向第二金属互连层延伸的钛/铝(TiAlx)芯。 在方法实施例中,去除半导体衬底的绝缘层的一部分以形成暴露下面的导电层的孔。 在孔的底部和侧壁上形成胶层,例如钛(Ti)层。 在孔中的胶层上形成Ti种子层。 在Ti种子层上形成含铝层。 将基底热处理以形成包括TiAlx芯的接触柱。

    Copper-plating elecrolyte containing polyvinylpyrrolidone and method for forming a copper interconnect
    3.
    发明授权
    Copper-plating elecrolyte containing polyvinylpyrrolidone and method for forming a copper interconnect 有权
    含有电解质电解质的聚乙烯吡咯烷酮和形成铜互连的方法

    公开(公告)号:US06607654B2

    公开(公告)日:2003-08-19

    申请号:US09899228

    申请日:2001-07-06

    IPC分类号: C25D338

    摘要: A copper-plating electrolyte includes an aqueous copper salt solution, a water-soluble &bgr;-naphtholethoxylate compound having the formula wherein n is an integer from 10 to 24, one selected from the group consisting of a disulfide having the formula XO3S(CH2)3SS(CH2)3SOX3 and a water-soluble mercaptopropanesulfonic acid or salt thereof having the formula HS(CH2)3SO3X, where X is sodium, potassium, or hydrogen, a water-soluble polyethylene glycol having a molecular weight ranging from about 4,600 to about 10,000, and a water-soluble polyvinylpyrrolidone having a molecular weight ranging from about 10,000 to about 1,300,000.

    摘要翻译: 镀铜电解质包括铜盐水溶液,具有方解石的水溶性β-萘基乙氧基化合物,n为10-24的整数,选自具有式XO 3 S(CH 2)3 SS的二硫化物 CH2)3SOX3和具有式HS(CH2)3SO3X的水溶性巯基丙磺酸或其盐,其中X为钠,钾或氢,分子量范围为约4,600至约10,000的水溶性聚乙二醇, 和分子量范围为约10,000至约1,300,000的水溶性聚乙烯吡咯烷酮。

    Semiconductor device having capacitor and method of manufacturing the same
    4.
    发明授权
    Semiconductor device having capacitor and method of manufacturing the same 失效
    具有电容器的半导体装置及其制造方法

    公开(公告)号:US06399457B2

    公开(公告)日:2002-06-04

    申请号:US09862733

    申请日:2001-05-21

    IPC分类号: H01L2120

    摘要: A semiconductor device having a capacitor. The capacitor includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. Each of the first and second metal nitride layers has a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less, to thereby reduce an equivalent oxide thickness of the dielectric layer.

    摘要翻译: 一种具有电容器的半导体器件。 电容器包括第一电极,由包括Ta 2 O 5层的金属氧化物层形成的电介质层和由顺序堆叠的第一和第二金属氮化物层构成的第二电极。 第一和第二金属氮化物层中的每一个具有TiN层和WN层。 电容器的第二电极是具有第一和第二金属氮化物层的双层结构,因此在750℃或更低的温度下进行形成第二电极之后的退火,从而降低电介质层的等效氧化物厚度 。

    Semiconductor device having capacitor and method of manufacturing the same
    5.
    发明授权
    Semiconductor device having capacitor and method of manufacturing the same 失效
    具有电容器的半导体装置及其制造方法

    公开(公告)号:US06261890B1

    公开(公告)日:2001-07-17

    申请号:US09209651

    申请日:1998-12-10

    IPC分类号: H01L218234

    摘要: The capacitor of semiconductor devices includes a first electrode, a dielectric layer formed of a metal oxide layer including a Ta2O5 layer, and a second electrode composed of first and second metal nitride layers sequentially stacked. First and second metal nitride layers are a TiN layer and a WN layer. The second electrode of the capacitor is a double-layered structure having the first and second metal nitride layers, and thus annealing after forming the second electrode is performed at 750° C. or less to avoid increasing an equivalent oxide thickness of the dielectric layer.

    摘要翻译: 半导体器件的电容器包括第一电极,由包括Ta 2 O 5层的金属氧化物层形成的电介质层和由顺序层叠的第一和第二金属氮化物层构成的第二电极。 第一和第二金属氮化物层是TiN层和WN层。 电容器的第二电极是具有第一和第二金属氮化物层的双层结构,因此在形成第二电极之后的退火在750℃以下进行,以避免增加电介质层的等效氧化物厚度。

    Method of manufacturing an electrical interconnection of a semiconductor device using an erosion protecting plug in a contact hole of interlayer dielectric layer
    6.
    发明授权
    Method of manufacturing an electrical interconnection of a semiconductor device using an erosion protecting plug in a contact hole of interlayer dielectric layer 有权
    使用层间电介质层的接触孔中的侵蚀保护插头制造半导体器件的电互连的方法

    公开(公告)号:US06372616B1

    公开(公告)日:2002-04-16

    申请号:US09670818

    申请日:2000-09-28

    IPC分类号: H01L213205

    CPC分类号: H01L21/76808

    摘要: A method of manufacturing an electrical interconnection of a semiconductor device produces an erosion protecting plug in a contact hole to protect a selected portion of an interlayer dielectric layer when the interlayer dielectric layer is being etched to form a recess for a conductive line. The contact hole is formed in the interlayer dielectric layer. The contact hole is filled with an organic material to form the erosion protecting plug. The organic material is a photoresist material or an organic polymer. A photoresist pattern is formed for exposing the erosion protecting plug and a portion of the interlayer dielectric layer adjacent to the erosion protecting plug. A recess which extends down to the contact hole is formed by etching the portion of the interlayer dielectric layer which is exposed by the photoresist pattern. The erosion protecting plug and the photoresist pattern are then removed. A conductive line filling the recess and a contact filling the contact hole are then formed.

    摘要翻译: 制造半导体器件的电互连的方法在接触孔中产生侵蚀保护插塞,以便在蚀刻层间电介质层以形成用于导电线的凹槽时保护层间电介质层的选定部分。 接触孔形成在层间电介质层中。 接触孔填充有机材料以形成侵蚀保护塞。 有机材料是光致抗蚀剂材料或有机聚合物。 形成光致抗蚀剂图案,用于暴露侵蚀保护塞和与侵蚀保护塞相邻的层间电介质层的一部分。 通过蚀刻由光致抗蚀剂图案曝光的层间电介质层的部分来形成向下延伸到接触孔的凹部。 然后去除侵蚀保护塞和光致抗蚀剂图案。 然后形成填充凹部的导电线和填充接触孔的触点。

    Stacked capacitors for integrated circuit devices and related methods
    7.
    发明授权
    Stacked capacitors for integrated circuit devices and related methods 失效
    用于集成电路器件的堆叠电容器及相关方法

    公开(公告)号:US5742472A

    公开(公告)日:1998-04-21

    申请号:US674883

    申请日:1996-07-03

    CPC分类号: H01L27/10852 H01L28/40

    摘要: A method for fabricating a capacitor on a substrate includes the steps of forming an insulating layer on the substrate, and forming the first plate electrode on the insulating layer. A first dielectric layer is then formed on the plate electrode, and a first common storage electrode is formed on the first dielectric layer. A contact hole is then formed through the insulating layer, the first plate electrode, the first dielectric layer, and the first common storage electrode, thereby exposing a predetermined portion of the substrate. A first spacer is formed on a sidewall of the contact hole, and a conductive plug is formed in the contact hole extending from the substrate to the first common storage electrode.

    摘要翻译: 在基板上制造电容器的方法包括以下步骤:在基板上形成绝缘层,并在绝缘层上形成第一平板电极。 然后在平板电极上形成第一电介质层,在第一电介质层上形成第一公共存储电极。 然后通过绝缘层,第一平板电极,第一介电层和第一公共存储电极形成接触孔,从而暴露基板的预定部分。 第一间隔件形成在接触孔的侧壁上,并且在从基板延伸到第一公共存储电极的接触孔中形成导电插塞。

    Methods for fabricating CVD TiN barrier layers for capacitor structures
    8.
    发明授权
    Methods for fabricating CVD TiN barrier layers for capacitor structures 失效
    制造用于电容器结构的CVD TiN阻挡层的方法

    公开(公告)号:US6010940A

    公开(公告)日:2000-01-04

    申请号:US935464

    申请日:1997-09-24

    摘要: A method of fabricating a capacitor for a integrated circuit device includes the steps of forming a lower capacitor electrode on an integrated circuit substrate, and forming a dielectric layer on the lower capacitor electrode opposite the integrated circuit substrate. A titanium nitride barrier layer is deposited by chemical vapor deposition on the dielectric layer opposite the integrated circuit substrate to a thickness in the range of 50 .ANG. to 500 .ANG. using TiCl.sub.4 as a source gas. The titanium nitride barrier layer is annealed, and an upper electrode is formed on the titanium nitride barrier layer opposite the integrated circuit substrate.

    摘要翻译: 一种制造用于集成电路器件的电容器的方法包括以下步骤:在集成电路衬底上形成下电容器电极,并在与集成电路衬底相对的下电容器电极上形成电介质层。 通过化学气相沉积将氮化钛阻挡层沉积在与集成电路衬底相对的电介质层上,使用TiCl 4作为源气体,其厚度范围为50纳米至500埃。 退火氮化钛阻挡层,在与集成电路基板相对的氮化钛阻挡层上形成上电极。