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    Method for Forming Dual Fully Silicided Gates and Devices with Dual Fully Silicided Gates
    1.
    发明申请
    Method for Forming Dual Fully Silicided Gates and Devices with Dual Fully Silicided Gates 审中-公开
    用于形成双层全硅酸盐浇口的双层完全硅酸盐浇口和设备的方法

    公开(公告)号：US20060263961A1

    公开(公告)日：2006-11-23

    申请号：US11382986

    申请日：2006-05-12

    申请人： Jorge Kittl ,  Anne Lauwers ,  Anabela Veloso ,  Anil Kottantharayil ,  Marcus van Dal

    发明人： Jorge Kittl ,  Anne Lauwers ,  Anabela Veloso ,  Anil Kottantharayil ,  Marcus van Dal

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823842 ,  H01L29/785

    摘要： A method for manufacturing CMOS devices with fully silicided (FUSI) gates is described. A metallic gate electrode of an NMOS transistor and a metallic gate electrode of a pMOS transistor have a different work function. The work function of each transistor type is determined by selecting a thickness of a corresponding semiconductor gate electrode and a thermal budget of a first thermal step such that, during silicidation, different silicide phases are obtained on the nMOS and the pMOS transistors. The work function of each type of transistor can be adjusted by selectively doping the semiconductor material prior to the formation of the silicide.

    摘要翻译： 描述了一种用于制造具有完全硅化（FUSI）栅极的CMOS器件的方法。 NMOS晶体管的金属栅电极和pMOS晶体管的金属栅电极具有不同的功函数。 通过选择对应的半导体栅电极的厚度和第一热步骤的热预算来确定每个晶体管类型的功函数，使得在硅化期间，在nMOS和pMOS晶体管上获得不同的硅化物相。 可以通过在形成硅化物之前选择性地掺杂半导体材料来调节每种类型的晶体管的功函数。

    Methods for manufacturing a CMOS device with dual dielectric layers
    7.
    发明申请
    Methods for manufacturing a CMOS device with dual dielectric layers 审中-公开
    制造具有双电介质层的CMOS器件的方法

    公开(公告)号：US20080191286A1

    公开(公告)日：2008-08-14

    申请号：US11972601

    申请日：2008-01-10

    申请人： Shou-Zen Chang ,  Hong Yu Yu ,  Anabela Veloso ,  Rita Vos ,  Stefan Kubicek ,  Serge Biesemans ,  Raghunath Singanamalla ,  Anne Lauwers ,  Bart Onsia

    发明人： Shou-Zen Chang ,  Hong Yu Yu ,  Anabela Veloso ,  Rita Vos ,  Stefan Kubicek ,  Serge Biesemans ,  Raghunath Singanamalla ,  Anne Lauwers ,  Bart Onsia

    IPC分类号： H01L27/00 ,  H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L29/785

    摘要： The present disclosure provides a dual workfunction semiconductor device and a method for manufacturing a dual workfunction semiconductor device. The method comprises providing a device on a first region and a device on a second region of a substrate. According to embodiments described herein, the method includes providing a dielectric layer onto the first and second region of the substrate, the dielectric layer on the first region being integrally deposited with the dielectric layer on the second region, and providing a gate electrode on top of the dielectric layer on both the first and second regions, the gate electrode on the first region being integrally deposited with the gate electrode on the second region. The method further includes changing the workfunction of the device on the first region by providing a capping layer onto the first region between the dielectric layer and the gate electrode, and changing the workfunction of the device on the second region by including species at the interface between the dielectric layer and the electrode.

    摘要翻译： 本公开提供了一种双功能半导体器件和用于制造双功能半导体器件的方法。 该方法包括在第一区域上提供器件和在衬底的第二区域上提供器件。 根据本文所述的实施例，该方法包括在基板的第一和第二区域上提供介电层，第一区域上的电介质层与第二区域上的电介质层整体沉积，并且在 所述第一区域和所述第二区域上的所述电介质层，所述第一区域上的所述栅电极与所述第二区域上的所述栅极电极整体地沉积。 该方法还包括通过在介电层和栅电极之间的第一区域上设置覆盖层来改变第一区域上的器件的功函数，以及通过在第二区域上的界面处包括物质来改变第二区域上的器件的功函数 介电层和电极。

    Semiconductor device and method for fabricating the same
    8.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08313993B2

    公开(公告)日：2012-11-20

    申请号：US12358188

    申请日：2009-01-22

    申请人： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

    发明人： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823857 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/513

    摘要： A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

    摘要翻译： 公开了一种双功能半导体器件及其制造方法。 一方面，一种器件包括在第一和第二衬底区域上的第一和第二晶体管。 第一和第二晶体管包括分别具有第一功函数的第一栅极堆叠和具有第二功函数的第二栅极堆叠。 第一和第二栅极堆叠各自包括主电介质，包括金属层的栅电极和它们之间的第二电介质覆盖层。 第二栅极堆叠还在主介质和金属层之间具有第一介电覆盖层。 选择金属层以确定第一功函数。 选择第一介电覆盖层以确定第二功函数。

    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20090184376A1

    公开(公告)日：2009-07-23

    申请号：US12358188

    申请日：2009-01-22

    申请人： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

    发明人： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

    IPC分类号： H01L27/092 ,  H01L21/28

    CPC分类号： H01L21/823857 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/513

    摘要： A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

    摘要翻译： 公开了一种双功能半导体器件及其制造方法。 一方面，一种器件包括在第一和第二衬底区域上的第一和第二晶体管。 第一和第二晶体管包括分别具有第一功函数的第一栅极堆叠和具有第二功函数的第二栅极堆叠。 第一和第二栅极堆叠各自包括主电介质，包括金属层的栅电极和它们之间的第二电介质覆盖层。 第二栅极堆叠还在主介质和金属层之间具有第一介电覆盖层。 选择金属层以确定第一功函数。 选择第一介电覆盖层以确定第二功函数。

    Method for gate electrode height control
    10.
    发明授权
    Method for gate electrode height control 有权
    栅电极高度控制方法

    公开(公告)号：US07709380B2

    公开(公告)日：2010-05-04

    申请号：US11645148

    申请日：2006-12-22

    申请人： Anabela Veloso

    发明人： Anabela Veloso

    IPC分类号： H01L21/44

    CPC分类号： H01L29/4975 ,  H01L21/28052 ,  H01L21/28097 ,  H01L21/823443 ,  H01L21/823456 ,  H01L21/823835 ,  H01L21/82385 ,  H01L29/66507 ,  H01L29/66545

    摘要： One inventive aspect relates to a method of controlling the gate electrode in a silicidation process. The method comprises applying a sacrificial cap layer on top of each of at least one gate electrode, each of the at least one gate electrode deposited with a given height on a semiconductor substrate. The method further comprises applying an additional layer of oxide on top of the sacrificial layer. The method further comprises covering with a material the semiconductor substrate provided with the at least one gate electrode having the sacrificial cap layer with the additional oxide layer on top. The method further comprises performing a CMP planarization step. The method further comprises removing at least the material and the additional layer of oxide until on top of each of the at least one gate electrode the sacrificial cap layer is exposed. The method further comprises removing the sacrificial cap layer from each of the at least one gate electrode, yielding each of the at least one gate electrode still having the given height.

    摘要翻译： 本发明的一个方面涉及在硅化工艺中控制栅电极的方法。 该方法包括在至少一个栅电极的每一个的顶部上施加牺牲覆盖层，所述至少一个栅电极中的每一个在半导体衬底上沉积给定的高度。 该方法还包括在牺牲层的顶部上施加附加的氧化物层。 该方法还包括用材料覆盖设置有具有牺牲帽层的至少一个栅电极的半导体衬底，顶部具有附加氧化物层。 该方法还包括执行CMP平坦化步骤。 该方法还包括至少去除氧化物的材料和附加层，直到在所述至少一个栅电极中的每一个上方覆盖牺牲覆盖层。 该方法还包括从至少一个栅极电极中的每个去除牺牲帽层，产生仍具有给定高度的至少一个栅极电极中的每一个。