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    Semiconductor product and method for forming a semiconductor product
    1.
    发明申请
    Semiconductor product and method for forming a semiconductor product 有权
    用于形成半导体产品的半导体产品和方法

    公开(公告)号：US20070048993A1

    公开(公告)日：2007-03-01

    申请号：US11217122

    申请日：2005-08-31

    申请人： Josef Willer ,  Patrick Haibach ,  Christoph Kleint ,  Nicolas Nagel

    发明人： Josef Willer ,  Patrick Haibach ,  Christoph Kleint ,  Nicolas Nagel

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11568

    摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.

    摘要翻译： 半导体产品包括具有基板表面的基板。 多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。 在字线之间提供多个导电接触结构。 该产品还包括多个填充结构。 每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。 两个相应的接触结构在第一方向上彼此间隔一定距离。 在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。 衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

    Method of forming contacts using auxiliary structures
    2.
    发明授权
    Method of forming contacts using auxiliary structures 有权
    使用辅助结构形成触点的方法

    公开(公告)号：US07416976B2

    公开(公告)日：2008-08-26

    申请号：US11217122

    申请日：2005-08-31

    申请人： Josef Willer ,  Patrick Haibach ,  Christoph Andreas Kleint ,  Nicolas Nagel

    发明人： Josef Willer ,  Patrick Haibach ,  Christoph Andreas Kleint ,  Nicolas Nagel

    IPC分类号： H01L21/44

    CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L27/115 ,  H01L27/11568

    摘要： A semiconductor product includes a substrate having a substrate surface. A plurality of wordlines are arranged at a distance from one another and running along a first direction. A plurality of conductive contact structures are provided between the wordlines. The product also includes a plurality of filling structures. Each filling structure separates from one another two respective contact structures arranged between two respective wordlines. The two respective contact structures are arranged at a distance from one another in the first direction. In the preferred embodiment, the contact structures have a top side provided at a distance from the substrate surface and extends to the substrate surface. The contact structures at the substrate surface have a width along the first direction that is larger than a width of the top sides of the contact structures along the first direction.

    摘要翻译： 半导体产品包括具有基板表面的基板。 多个字线被布置成彼此间隔一定距离并沿着第一方向延伸。 在字线之间提供多个导电接触结构。 该产品还包括多个填充结构。 每个填充结构彼此分开布置在两个相应字线之间的两个相应的接触结构。 两个相应的接触结构在第一方向上彼此间隔一定距离。 在优选实施例中，接触结构具有设置在离基板表面一定距离处并且延伸到基板表面的顶侧。 衬底表面处的接触结构具有沿着第一方向的宽度，该宽度大于沿着第一方向的接触结构的顶侧宽度。

    Interconnection structure and method of manufacturing the same
    4.
    发明授权
    Interconnection structure and method of manufacturing the same 有权
    互连结构及制造方法

    公开(公告)号：US07462038B2

    公开(公告)日：2008-12-09

    申请号：US11676622

    申请日：2007-02-20

    申请人： Roman Knoefler ,  Christoph Kleint ,  Steffen Meyer ,  Nicolas Nagel

    发明人： Roman Knoefler ,  Christoph Kleint ,  Steffen Meyer ,  Nicolas Nagel

    IPC分类号： H01R12/00

    CPC分类号： H01R13/22

    摘要： An interconnection structure includes two staggered contact rows of evenly spaced contacts. Each contact row extends along a first direction. The interconnection structure further includes conductive lines extending along a second direction that intersects the first direction. The interconnection structure further includes intermediate contacts, where each intermediate contact is in contact with one of the contacts and one of the conductive lines.

    摘要翻译： 互连结构包括具有均匀间隔的接触的两个交错的接触排。 每个接触排沿第一方向延伸。 互连结构还包括沿着与第一方向相交的第二方向延伸的导电线。 互连结构还包括中间触点，其中每个中间触点与触点之一和导线中的一个接触。

    INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME
    6.
    发明申请
    INTERCONNECTION STRUCTURE AND METHOD OF MANUFACTURING THE SAME 有权
    互连结构及其制造方法

    公开(公告)号：US20080200046A1

    公开(公告)日：2008-08-21

    申请号：US11676622

    申请日：2007-02-20

    申请人： Roman Knoefler ,  Christoph Kleint ,  Steffen Meyer ,  Nicolas Nagel

    发明人： Roman Knoefler ,  Christoph Kleint ,  Steffen Meyer ,  Nicolas Nagel

    IPC分类号： H01R12/00

    CPC分类号： H01R13/22

    摘要： An interconnection structure includes two staggered contact rows of evenly spaced contacts. Each contact row extends along a first direction. The interconnection structure further includes conductive lines extending along a second direction that intersects the first direction. The interconnection structure further includes intermediate contacts, where each intermediate contact is in contact with one of the contacts and one of the conductive lines.

    摘要翻译： 互连结构包括具有均匀间隔的接触的两个交错的接触排。 每个接触排沿第一方向延伸。 互连结构还包括沿着与第一方向相交的第二方向延伸的导电线。 互连结构还包括中间触点，其中每个中间触点与触点之一和导线中的一个接触。

    Method of manufacturing at least one semiconductor component and memory cells
    7.
    发明申请
    Method of manufacturing at least one semiconductor component and memory cells 有权
    制造至少一个半导体部件和存储单元的方法

    公开(公告)号：US20080009115A1

    公开(公告)日：2008-01-10

    申请号：US11483968

    申请日：2006-07-10

    申请人： Josef Willer ,  Nicolas Nagel

    发明人： Josef Willer ,  Nicolas Nagel

    IPC分类号： H01L21/336

    CPC分类号： H01L29/7881 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11568 ,  H01L29/792

    摘要： A method of manufacturing at least one NAND-coupled semiconductor component is disclosed. A layer structure is formed on or above a semiconductor substrate. The layer structure is patterned to expose at least one region to be doped. The exposed region is doped and annealed. The patterned layer structure is at least partially removed. Replacing material is formed in the region in which the patterned layer structure has been removed, thereby forming the at least one NAND-coupled semiconductor component.

    摘要翻译： 公开了制造至少一个NAND耦合的半导体部件的方法。 在半导体衬底上或上方形成层结构。 图案化层结构以暴露待掺杂的至少一个区域。 曝光区域被掺杂并退火。 图案化层结构至少部分地被去除。 在去除图案层结构的区域中形成更换材料，从而形成至少一个NAND耦合的半导体部件。

    Memory cell arrangements
    8.
    发明授权
    Memory cell arrangements 有权
    存储单元布置

    公开(公告)号：US07838921B2

    公开(公告)日：2010-11-23

    申请号：US11526149

    申请日：2006-09-22

    申请人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    发明人： Josef Willer ,  Thomas Mikolajick ,  Nicolas Nagel ,  Michael Specht

    IPC分类号： H01L29/788

    CPC分类号： H01L27/105 ,  H01L27/11526 ,  H01L27/11529

    摘要： A memory cell arrangement includes a first memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells, a second memory cell string having a plurality of serially source-to-drain-coupled transistors, at least some of them being memory cells. A dielectric material is between and above the first memory cell string and the second memory cell string. A source/drain line groove is defined in the dielectric material. The source/drain line groove extends from a source/drain region of one transistor of the first memory cell string to a source/drain region of the second memory cell string. Electrically conductive filling material is disposed in the source/drain line groove. Dielectric filling material is disposed in the source/drain line groove between the source/drain regions.

    摘要翻译： 存储单元布置包括具有多个串联的源极至漏极耦合的晶体管的第一存储单元串，其中至少一些是存储单元;第二存储单元串，具有多个串联的源至漏耦合的晶体管 晶体管，其中至少有一些是存储单元。 电介质材料在第一存储单元串和第二存储单元串之间和之上。 源极/漏极线沟槽限定在电介质材料中。 源极/漏极线槽从第一存储单元串的一个晶体管的源极/漏极区域延伸到第二存储单元串的源极/漏极区域。 导电填充材料设置在源极/漏极线槽中。 电介质填充材料设置在源极/漏极区域之间的源极/漏极线沟槽中。

    Semiconductor memory device and method of operating a semiconductor memory device
    10.
    发明申请
    Semiconductor memory device and method of operating a semiconductor memory device 审中-公开
    半导体存储器件和操作半导体存储器件的方法

    公开(公告)号：US20070231991A1

    公开(公告)日：2007-10-04

    申请号：US11396398

    申请日：2006-03-31

    申请人： Josef Willer ,  Nicolas Nagel ,  Thomas Mikolajick ,  Karl-Heinz Kuesters

    发明人： Josef Willer ,  Nicolas Nagel ,  Thomas Mikolajick ,  Karl-Heinz Kuesters

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/792 ,  G11C16/0475 ,  G11C16/14 ,  G11C16/16

    摘要： A semiconductor memory device includes a channel region, a gate electrode adjacent the channel region, and a charge-trapping layer between the channel region and the gate electrode. A voltage is applied between the gate electrode and the channel region to cause a first current of a first kind of charge carriers from the channel region to move into the charge-trapping layer and to cause a second current of a second kind of charge carriers from the gate electrode to move into the charge-trapping layer, until the value of the second current is at least half the amount of the first current value.

    摘要翻译： 半导体存储器件包括沟道区，与沟道区相邻的栅电极以及沟道区和栅电极之间的电荷俘获层。 在栅极电极和沟道区域之间施加电压，使来自沟道区域的第一种电荷载流子的第一电流移动到电荷俘获层中，并引起第二种载流子的第二电流 栅电极移动到电荷捕获层中，直到第二电流的值至少为第一电流值的一半。