公开(公告)号：US20110212593A1

公开(公告)日：2011-09-01

申请号：US13036201

申请日：2011-02-28

申请人： Joseph Damian Gordon Lacey ,  Thomas L. Maguire ,  Vikram Joshi ,  Dennis J. Yost

发明人： Joseph Damian Gordon Lacey ,  Thomas L. Maguire ,  Vikram Joshi ,  Dennis J. Yost

IPC分类号： H01L21/02

CPC分类号： B81C1/00095 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0104

摘要： The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.

摘要翻译： 本发明一般涉及在线路（BEOL）工艺的互补金属氧化物半导体（CMOS）后端中形成微机电系统（MEMS）悬臂开关。 悬臂开关形成为与结构中的下电极电连通。 下电极可以是毯式沉积和图案化或简单地沉积在底层结构的通孔或沟槽中。 然后通过化学机械抛光或平面化（CMP）将用于下电极的多余材料平坦化。 然后在平坦化的下电极上形成悬臂开关。

公开(公告)号：US08124527B2

公开(公告)日：2012-02-28

申请号：US13036201

申请日：2011-02-28

申请人： Joseph Damian Gordon Lacey ,  Thomas L. Maguire ,  Vikram Joshi ,  Dennis J. Yost

发明人： Joseph Damian Gordon Lacey ,  Thomas L. Maguire ,  Vikram Joshi ,  Dennis J. Yost

IPC分类号： H01L21/4763

CPC分类号： B81C1/00095 ,  B81B2203/04 ,  B81B2207/07 ,  B81C1/00611 ,  B81C2201/0104

摘要： The present invention generally relates to the formation of a micro-electromechanical system (MEMS) cantilever switch in a complementary metal oxide semiconductor (CMOS) back end of the line (BEOL) process. The cantilever switch is formed in electrical communication with a lower electrode in the structure. The lower electrode may be either blanket deposited and patterned or simply deposited in vias or trenches of the underlying structure. The excess material used for the lower electrode is then planarized by chemical mechanical polishing or planarization (CMP). The cantilever switch is then formed over the planarized lower electrode.

摘要翻译： 本发明一般涉及在线路（BEOL）工艺的互补金属氧化物半导体（CMOS）后端中形成微机电系统（MEMS）悬臂开关。 悬臂开关形成为与结构中的下电极电连通。 下电极可以是毯式沉积和图案化或简单地沉积在底层结构的通孔或沟槽中。 然后通过化学机械抛光或平面化（CMP）将用于下电极的多余材料平坦化。 然后在平坦化的下电极上形成悬臂开关。

公开(公告)号：US5635428A

公开(公告)日：1997-06-03

申请号：US329108

申请日：1994-10-25

申请人： Patrick M. Martin ,  Dennis J. Yost

发明人： Patrick M. Martin ,  Dennis J. Yost

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/316 ,  H01L21/02

CPC分类号： H01L23/5329 ,  H01L21/76819 ,  H01L2924/0002

摘要： A semiconductor device includes conductor regions 24 and 26 on a layer of the semiconductor device; a first insulator layer 28 over and between the conductor regions 24 and 26; polyimide regions 30, 32, and 34 over the first insulator layer 28 in gaps between the conductor regions 24 and 26; and a second insulator layer 38 over the first insulator layer 28 and over the polyimide regions 30, 32, and 34. A surface of the second insulator layer 38 is substantially planar.

摘要翻译： 半导体器件在半导体器件的层上包括导体区域24和26; 在导体区域24和26之间和之间的第一绝缘体层28; 在导体区域24和26之间的间隙中的第一绝缘体层28上的聚酰亚胺区域30,32和34; 以及在第一绝缘体层28上方以及聚酰亚胺区域30,32和34之上的第二绝缘体层38.第二绝缘体层38的表面基本上是平面的。

公开(公告)号：US07332360B2

公开(公告)日：2008-02-19

申请号：US10973552

申请日：2004-10-25

申请人： Michael C. Smayling ,  Dennis J. Yost

发明人： Michael C. Smayling ,  Dennis J. Yost

IPC分类号： G01R31/26 ,  H01L21/66

CPC分类号： H01L22/12 ,  H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention generally provides an apparatus and a method for inspecting a substrate in a substrate processing system. In one aspect, a voltage or current source is used in conjunction with a power density receiving device, such as a spectrometer, to inspect a substrate for various noise spectrum signatures. In one embodiment, spectral data collected from a given substrate is used to generate a current or voltage spectral signature. This spectral signature may then be compared to a reference spectral density signature to predict reliability of a feature structure of a substrate in processing and feedback to the substrate processing system for substrate processing control. Embodiments of the invention further include computer-readable media containing instructions for controlling the substrate processing system, and computer program products having computer-readable program code embodied therein for controlling the substrate processing system and inspecting defects on semiconductor features.

摘要翻译： 本发明总体上提供了一种用于检查衬底处理系统中的衬底的装置和方法。 在一个方面，电压源或电流源与诸如光谱仪的功率密度接收装置结合使用，以检查衬底以进行各种噪声谱特征。 在一个实施例中，从给定衬底收集的光谱数据用于产生电流或电压光谱特征。 然后可以将该光谱特征与参考光谱密度特征进行比较，以预测处理中的衬底的特征结构的可靠性并反馈给用于衬底处理控制的衬底处理系统。 本发明的实施例还包括包含用于控制基板处理系统的指令的计算机可读介质，以及其中包含用于控制基板处理系统和检查半导体特征缺陷的计算机可读程序代码的计算机程序产品。

公开(公告)号：US5444018A

公开(公告)日：1995-08-22

申请号：US135863

申请日：1993-10-13

申请人： Dennis J. Yost ,  Thomas D. Bonifield ,  Roc Blumenthal

发明人： Dennis J. Yost ,  Thomas D. Bonifield ,  Roc Blumenthal

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522 ,  H01L21/441

CPC分类号： H01L21/28512 ,  H01L21/76895 ,  H01L2924/0002

摘要： A contact for a semiconductor device has a via extending through a dielectric and collimated titanium in the via. Depositing titanium by collimation places sufficient metal into high aspect ratio contacts to make good electrical connection. The collimated titanium may be reacted in a nitrogen containing ambient to form a titanium silicide layer at the bottom of the contact and a titanium nitride layer over the titanium silicide layer. The titanium silicide layer provides good electrical contact to a device in a silicon semiconductor substrate and lowers contact resistance. Tungsten may be deposited over the colliminated titanium to form a conductor layer. The titanium nitride layer provides a sticking layer for the tungsten. The contact structure and the method are useful in high aspect ratio contacts present in VLSI multilevel interconnected devices such as dynamic random access memories.

摘要翻译： 用于半导体器件的触点具有延伸穿过通孔中的电介质和准直钛的通孔。 通过准直沉积钛将足够的金属置入高纵横比触点，以实现良好的电连接。 准直的钛可以在含氮环境中反应以在接触的底部形成硅化钛层，并且在钛硅化物层上方形成氮化钛层。 硅化钛层与硅半导体衬底中的器件提供良好的电接触并降低接触电阻。 钨可以沉积在准直钛上以形成导体层。 氮化钛层为钨提供粘附层。 接触结构和方法对于存在于VLSI多级互连设备（例如动态随机存取存储器）中的高纵横比触点是有用的。

公开(公告)号：US20080230092A1

公开(公告)日：2008-09-25

申请号：US11690405

申请日：2007-03-23

申请人： Alexander Sou-Kang Ko ,  Jianshe Tang ,  Brian J. Brown ,  Richard R. Endo ,  Steven Verhaverbeke ,  Cole Franklin ,  Dennis J. Yost ,  Runzi Chang

发明人： Alexander Sou-Kang Ko ,  Jianshe Tang ,  Brian J. Brown ,  Richard R. Endo ,  Steven Verhaverbeke ,  Cole Franklin ,  Dennis J. Yost ,  Runzi Chang

IPC分类号： B08B3/00

CPC分类号： B08B7/00 ,  B08B3/024 ,  B08B3/08 ,  H01L21/67051

摘要： A single-substrate cleaning apparatus and method of use are described. In an embodiment of the present invention, a liquid cleaning solution is dispensed in small volumes to form a substantially uniform static liquid layer over a substrate surface by atomizing the viscous liquid with an inert gas in a two-phase nozzle. In another embodiment of the present invention, after a layer of the cleaning solution is formed over the substrate to be cleaned, acoustic energy is applied to the substrate to improve the cleaning efficiency. In a further embodiment, cleaning solution precipitates are avoided by dispensing de-ionized water with a spray nozzle to gradually dilute the cleaning solution prior to dispensing de-ionized water with a stream nozzle.

摘要翻译： 对单基板清洗装置及其使用方法进行说明。 在本发明的一个实施例中，通过在两相喷嘴中用惰性气体雾化粘性液体，以小体积分配液体清洗溶液以在基板表面上形成基本均匀的静态液体层。 在本发明的另一个实施方案中，在将清洁溶液层形成在要清洁的基底上之后，将声能施加到基底以提高清洁效率。 在另一个实施方案中，通过用喷嘴分配去离子水以在用流喷嘴分配去离子水之前逐渐稀释清洁溶液来避免清洁溶液沉淀物。

公开(公告)号：US07313456B2

公开(公告)日：2007-12-25

申请号：US10818929

申请日：2004-04-05

申请人： John H. Madok ,  Dennis J. Yost ,  Robin W. Cheung

发明人： John H. Madok ,  Dennis J. Yost ,  Robin W. Cheung

IPC分类号： G06F19/00

CPC分类号： G06F17/50 ,  G06Q10/06312 ,  G06Q10/06395

摘要： A method and apparatus for capturing and using design intent within an IC fabrication process. The design intent information is produced along with the design release by a design company. The design release and design intent information are coupled to an IC manufacturing facility where the design release is used for producing the layout of the integrated circuit and the design intent information is coupled to the equipment, especially the metrology equipment, within the IC manufacturing facility. As such, the design intent information can be used to optimize processing during IC fabrication to achieve optimization of the critical characteristics intended by the designer.

摘要翻译： 一种用于在IC制造过程中捕获和使用设计意图的方法和装置。 设计意图信息与设计公司的设计发布一起生成。 设计发布和设计意图信息耦合到IC制造设备，其中设计版本用于生成集成电路的布局，并且设计意图信息耦合到IC制造设备内的设备，特别是计量设备。 因此，可以使用设计意图信息来优化IC制造过程中的处理，以实现设计者所要求的关键特性的优化。

公开(公告)号：US5508233A

公开(公告)日：1996-04-16

申请号：US329021

申请日：1994-10-25

申请人： Dennis J. Yost ,  Patrick M. Martin

发明人： Dennis J. Yost ,  Patrick M. Martin

IPC分类号： H01L21/3105 ,  H01L21/768 ,  H01L21/465

CPC分类号： H01L21/31051 ,  H01L21/76819

摘要： A method for planarizing the surface of a layer in a semiconductor device includes forming conductor regions 24, 26, and 28 on a layer of the semiconductor device; forming first insulator regions 30, 32, and 34 in gaps between the conductor regions 24, 26, and 28; and forming an insulator layer 40 over the first insulator regions 30, 32, and 34, and over the conductor regions 24, 26, and 28 such that a surface of the insulator layer 40 will be substantially planar.

摘要翻译： 用于平坦化半导体器件中的层的表面的方法包括在半导体器件的层上形成导体区域24,26和28; 在导体区域24,26和28之间的间隙中形成第一绝缘体区域30,32和34; 以及在第一绝缘体区域30,32和34之上以及在导体区域24,26和28之上形成绝缘体层40，使得绝缘体层40的表面将基本上是平面的。