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12 条记录 (耗时 0.021 秒)

    Characterizing multi-port cascaded networks
    6.
    发明授权
    Characterizing multi-port cascaded networks 失效
    表征多端口级联网络

    公开(公告)号：US06785625B1

    公开(公告)日：2004-08-31

    申请号：US10145856

    申请日：2002-05-14

    申请人： Jun Fan ,  Arthur R. Alexander ,  James L. Knighten ,  Norman W. Smith

    发明人： Jun Fan ,  Arthur R. Alexander ,  James L. Knighten ,  Norman W. Smith

    IPC分类号： G01R2728

    CPC分类号： G01R27/28

    摘要： A test mechanism includes test equipment to measure frequency-domain data, such as scattering or S parameters. The S parameters are transformed to a different type of network parameters, such as transmission or T parameters. Contributions of test fixtures can be easily removed for the overall T-parameter matrix of a device under test connected in cascade with the test fixture. The test mechanism provides accurate measurement of a device under test represented by a multi-port (greater than two ports) network that is cascaded with another multi-port network representing the test fixture.

    摘要翻译： 测试机制包括测量频域数据的测试设备，如散射或S参数。 S参数被转换为不同类型的网络参数，如传输或T参数。 对于与测试夹具级联连接的被测器件的整体T参数矩阵，测试夹具的贡献可以轻松消除。 测试机制提供对被测试设备进行精确测量，由多端口（大于两个端口）网络级联，并与代表测试夹具的另一个多端口网络级联​​。

    Enhancing signal path characteristics in a circuit board
    7.
    发明授权
    Enhancing signal path characteristics in a circuit board 有权
    增强电路板中的信号路径特性

    公开(公告)号：US07045719B1

    公开(公告)日：2006-05-16

    申请号：US10274573

    申请日：2002-10-21

    申请人： Arthur R. Alexander ,  James L. Knighten ,  Jun Fan

    发明人： Arthur R. Alexander ,  James L. Knighten ,  Jun Fan

    IPC分类号： H01R12/04

    CPC分类号： H05K1/0251 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/09327 ,  H05K2201/09718 ,  Y10T29/49165

    摘要： A circuit board includes multiple signal layers, in which signal lines are routed, and power reference plane layers, in which power reference planes (e.g., power supply voltage or ground) are provided. Vias are passed through at least one signal layer and at least one power reference plane layer, or alternatively, vias are passed through at least two power reference plane layers. In one arrangement, a first clearance is defined around the via at the signal layer and a second clearance is defined around the via at the power reference plane layer. The second clearance is larger in size than the first clearance to match or tailor the impedance of the via as closely as possible with the impedance of the signal line that the via is electrically connected to. In another arrangement, clearances around vias at different power reference plane layers are selected to have different sizes to enhance the ability of one of the power reference plane layers (the one with a smaller clearance size) to carry a higher current level.

    摘要翻译： 电路板包括其中信号线路由的多个信号层和功率参考平面层，其中提供功率参考平面（例如，电源电压或地）。 通孔通过至少一个信号层和至少一个功率参考平面层，或者替代地，通孔穿过至少两个功率参考平面层。 在一种布置中，在信号层周围围绕通孔限定第一间隙，并且在功率参考平面层周围的通孔周围限定第二间隙。 第二间隙的尺寸大于第一间隙，以便匹配或调整通孔的阻抗尽可能接近通孔电连接到的信号线的阻抗。 在另一种布置中，选择不同功率参考平面层上的通孔周围的间隙以具有不同的尺寸以增强功率参考平面层（具有较小的间隙尺寸的一个）之一的能力承载更高的电流水平。

    Tailoring via impedance on a circuit board
    8.
    发明授权
    Tailoring via impedance on a circuit board 失效
    通过电路板上的阻抗进行裁剪

    公开(公告)号：US07435912B1

    公开(公告)日：2008-10-14

    申请号：US10145436

    申请日：2002-05-14

    申请人： Arthur R. Alexander ,  James L. Knighten ,  Jun Fan

    发明人： Arthur R. Alexander ,  James L. Knighten ,  Jun Fan

    IPC分类号： H01R12/04 ,  H05K1/11

    CPC分类号： H05K1/0251 ,  H05K1/0298 ,  H05K1/116 ,  H05K1/185 ,  H05K3/429 ,  H05K2201/09327 ,  H05K2201/09718 ,  Y10T29/49165

    摘要： A circuit board includes multiple signal layers, in which signal lines are routed, and reference plane layers, in which power reference planes are provided. To connect signal lines at different signal layers, vias are passed through at least one signal layer and at least one reference plane layer. At the one signal layer, a first clearance (or anti-pad) is defined around the via. At the reference plane layer, a second clearance is defined around the via. The second clearance is larger in size than the first clearance to match the impedance of the via as closely as possible with the impedance of a signal line the via is electrically connected to.

    摘要翻译： 电路板包括信号线路由的多个信号层以及提供功率参考平面的参考平面层。 为了在不同的信号层连接信号线，通孔通过至少一个信号层和至少一个参考平面层。 在一个信号层处，围绕通孔限定第一间隙（或抗焊盘）。 在参考平面层，围绕通孔限定第二间隙。 第二间隙的尺寸大于第一间隙，以使通孔的阻抗尽可能接近通孔电连接到的信号线的阻抗。

    Providing shields to reduce electromagnetic interference from connectors
    9.
    发明授权
    Providing shields to reduce electromagnetic interference from connectors 失效
    提供屏蔽以减少连接器的电磁干扰

    公开(公告)号：US06887105B2

    公开(公告)日：2005-05-03

    申请号：US09881464

    申请日：2001-06-14

    申请人： James L. Knighten ,  Arthur R. Alexander

    发明人： James L. Knighten ,  Arthur R. Alexander

    IPC分类号： H01R13/648 ,  H01R13/52 ,  H01R13/6473 ,  H01R13/6592 ,  H01R13/6596 ,  H01R13/73 ,  H01R13/74 ,  H01R9/03

    CPC分类号： H01R13/6473 ,  H01R13/5213 ,  H01R13/6592 ,  H01R13/6596 ,  H01R13/746 ,  Y10S439/939

    摘要： A method and apparatus to provide a shield assembly for a connector, with the shield assembly having a cover to enclose the connector and a neck portion adapted to surround an outer surface of a portion of the cable. An inner surface of the neck portion makes contact with the outer surface of the cable. When the cable carries a high frequency signal, a capacitive impedance is provided between the neck portion and an outer shield of the cable to reduce electromagnetic signal leakage. Alternatively, the neck portion can make electrical contact with the cable shield, either by use of elements protruding from the inner surface of the neck portion or by removing an insulating jacket of the cable.

    摘要翻译： 一种提供用于连接器的屏蔽组件的方法和装置，其中屏蔽组件具有盖以封闭连接器，以及适于围绕电缆的一部分的外表面的颈部。 颈部的内表面与电缆的外表面接触。 当电缆承载高频信号时，在电缆的颈部和外屏蔽之间提供电容性阻抗以减少电磁信号泄漏。 或者，颈部可以通过使用从颈部的内表面突出的元件或通过去除电缆的绝缘护套而与电缆屏蔽件电接触。

    Side plated electromagnetic interference shield strip for a printed circuit board
    10.
    发明授权
    Side plated electromagnetic interference shield strip for a printed circuit board 失效
    用于印刷电路板的侧面电磁干扰屏蔽条

    公开(公告)号：US5586011A

    公开(公告)日：1996-12-17

    申请号：US297346

    申请日：1994-08-29

    申请人： Arthur R. Alexander

    发明人： Arthur R. Alexander

    IPC分类号： H05K1/00 ,  H05K1/02 ,  H05K9/00

    CPC分类号： H05K9/0039 ,  H05K1/0218 ,  H05K1/0298

    摘要： An electric circuit board including EMI shielding. The board comprises a substrate including top and bottom surfaces and at least one internal ground layer, the internal ground layer being electrically insulated from the external surfaces of the substrate. A plurality of vias are formed in the substrate near the edges of the substrate, each via providing an opening from the surface of the substrate to the internal ground layer A metal plating is applied to the vias, the edges of the substrate and the perimeter of the surface of the substrate, the metal plating along the substrate perimeter being applied over the plated-up vias to electrically connect the ground plane with the metal plating applied to the edges of the substrate.

    摘要翻译： 包括EMI屏蔽的电路板。 该基板包括一个包括顶面和底面以及至少一个内部接地层的基板，该内部接地层与该基板的外表面电绝缘。 在基板的靠近基板的边缘处形成多个通孔，每个通孔提供从基板的表面到内部接地层A的开口。金属镀层被施加到通孔，基板的边缘和周边 衬底的表面，沿着衬底周边的金属电镀施加在电镀通孔上，以将接地平面与施加到衬底的边缘的金属电镀电连接。