公开(公告)号：US06700153B2

公开(公告)日：2004-03-02

申请号：US10136385

申请日：2002-05-02

申请人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

发明人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10855 ,  Y10T29/5111

摘要： An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

公开(公告)号：US06911364B2

公开(公告)日：2005-06-28

申请号：US10687838

申请日：2003-10-20

申请人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

发明人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10855

摘要： An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

摘要翻译： 在层间绝缘层的表面上方和在从层间绝缘层的表面的深度延伸的导电插塞的表面之上形成蚀刻停止层。 在蚀刻停止层上沉积下模层，并且通过在形成下模层期间向下模层添加掺杂剂并且通过对下模层进行退火来调节下模层的湿蚀刻速率。 然后将上模层沉积在下模层的表面上，使得上模层的湿蚀刻速率小于下模层的经调整的湿蚀刻速率。 然后对上模层，下模层和蚀刻停止层进行干蚀刻以在其中形成露出接触塞表面的至少一部分的开口。 然后进行上模层和下模层的湿式蚀刻，以便增加下模层上开口的尺寸，从而暴露出邻近导电塞表面的蚀刻停止层的表面部分 。 然后将导电材料沉积在上模具层和下模层中的开口的表面上，以限定电容器电极。

公开(公告)号：US20050170603A1

公开(公告)日：2005-08-04

申请号：US11024981

申请日：2004-12-30

申请人： Wook Lee ,  In-Seak Hwang ,  Yong-Sun Ko ,  Ki-Hyun Hwang

发明人： Wook Lee ,  In-Seak Hwang ,  Yong-Sun Ko ,  Ki-Hyun Hwang

IPC分类号： H01L21/8242 ,  H01L21/02 ,  H01L21/20

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/91

摘要： A method for forming a capacitor for use in a semiconductor device having electrode plugs surrounded by an insulating film and connected to underlying contact pads, includes sequentially forming an etch stop film and a mold oxide film on the insulating film and the electrode plugs, forming recesses in portions of the mold oxide film and the etching stopper film, the recesses exposing the electrode plugs, forming storage node electrodes in the recesses, filling the recesses in which the storage node electrodes are formed with an artificial oxide film, planarizing the storage node electrodes and the artificial oxide film so that the storage node electrodes are separated from one another, and selectively removing the mold oxide film and the artificial oxide film using a diluted hydrofluoric acid solution containing substantially no ammonium bifluoride.

摘要翻译： 一种用于形成用于半导体器件的电容器的方法，所述半导体器件具有由绝缘膜包围并连接到下面的接触焊盘的电极塞，包括在所述绝缘膜和所述电极插塞上顺序地形成蚀刻停止膜和模制氧化物膜， 在模具氧化膜和蚀刻停止膜的部分中，露出电极塞的凹部，在凹部中形成存储节点电极，用存储节点电极填充形成有人造氧化膜的凹部，使存储节点电极平坦化 和人造氧化物膜，使得储存节点电极彼此分离，并且使用基本上不含氟化二氢铵的稀释的氢氟酸溶液选择性地除去模制氧化物膜和人造氧化物膜。

公开(公告)号：US07361547B2

公开(公告)日：2008-04-22

申请号：US11024981

申请日：2004-12-30

申请人： Kwang Wook Lee ,  In-Seak Hwang ,  Yong-Sun Ko ,  Ki-Hyun Hwang

发明人： Kwang Wook Lee ,  In-Seak Hwang ,  Yong-Sun Ko ,  Ki-Hyun Hwang

IPC分类号： H01L21/8242

CPC分类号： H01L28/84 ,  H01L27/10852 ,  H01L28/91

摘要： A method for forming a capacitor for use in a semiconductor device having electrode plugs surrounded by an insulating film and connected to underlying contact pads, includes sequentially forming an etch stop film and a mold oxide film on the insulating film and the electrode plugs, forming recesses in portions of the mold oxide film and the etching stopper film, the recesses exposing the electrode plugs, forming storage node electrodes in the recesses, filling the recesses in which the storage node electrodes are formed with an artificial oxide film, planarizing the storage node electrodes and the artificial oxide film so that the storage node electrodes are separated from one another, and selectively removing the mold oxide film and the artificial oxide film using a diluted hydrofluoric acid solution containing substantially no ammonium bifluoride.

摘要翻译： 一种用于形成用于半导体器件的电容器的方法，所述半导体器件具有由绝缘膜包围并连接到下面的接触焊盘的电极塞，包括在所述绝缘膜和所述电极插塞上顺序地形成蚀刻停止膜和模制氧化物膜， 在模具氧化膜和蚀刻停止膜的部分中，露出电极塞的凹部，在凹部中形成存储节点电极，用存储节点电极填充形成有人造氧化膜的凹部，使存储节点电极平坦化 和人造氧化物膜，使得储存节点电极彼此分离，并且使用基本上不含氟化二氢铵的稀释的氢氟酸溶液选择性地除去模制氧化物膜和人造氧化物膜。

公开(公告)号：US07119029B2

公开(公告)日：2006-10-10

申请号：US10839501

申请日：2004-05-05

申请人： Won-Sik Shin ,  Ki-Hyun Hwang ,  Jung-Hwan Oh ,  Hyeon-Deok Lee ,  Seok-Woo Nam

发明人： Won-Sik Shin ,  Ki-Hyun Hwang ,  Jung-Hwan Oh ,  Hyeon-Deok Lee ,  Seok-Woo Nam

IPC分类号： H01L23/48

CPC分类号： H01L21/02238 ,  C23C8/12 ,  C23C8/28 ,  H01L21/02178 ,  H01L21/02181 ,  H01L21/3144

摘要： In a method of forming an oxide layer, ozone is generated by reacting an oxygen gas having a first flow rate with a nitrogen gas having a second flow rate of more than about 1% of the first flow rate. A reactant including the ozone and nitrogen is provided onto a silicon substrate. A surface of the silicon substrate is oxidized via the reaction of the reactant with silicon in the silicon substrate. The flow rate of the nitrogen gas is increased while ozone serving as an oxidant is formed by reacting the nitrogen gas with the oxygen gas. Thus, the oxide layer or a metal oxide layer including nitrogen may be rapidly formed on the substrate.

摘要翻译： 在形成氧化物层的方法中，通过使具有第一流量的氧气与具有大于第一流量的约1％的第二流量的氮气反应来生成臭氧。 将包含臭氧和氮的反应物提供到硅衬底上。 硅衬底的表面通过反应物与硅衬底中的硅的反应被氧化。 通过使氮气与氧气反应而形成臭氧作为氧化剂，氮气的流量增加。 因此，可以在衬底上快速形成包含氮的氧化物层或金属氧化物层。

公开(公告)号：US09240357B2

公开(公告)日：2016-01-19

申请号：US14100651

申请日：2013-12-09

申请人： Tae-Gon Kim ,  Jong-Hoon Kang ,  Jae-Young Ahn ,  Jun-Kyu Yang ,  Han-Mei Choi ,  Ki-Hyun Hwang

发明人： Tae-Gon Kim ,  Jong-Hoon Kang ,  Jae-Young Ahn ,  Jun-Kyu Yang ,  Han-Mei Choi ,  Ki-Hyun Hwang

IPC分类号： H01L21/66 ,  H01L21/265 ,  H01L21/311 ,  H01L27/115

CPC分类号： H01L22/12 ,  H01L21/31116 ,  H01L22/20 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to example embodiments of inventive concepts, a method of fabricating a semiconductor device includes: forming a preliminary stack structure, the preliminary stack structure defining a through hole; forming a protection layer and a dielectric layer in the through hole; forming a channel pattern, a gapfill pattern, and a contact pattern in the through hole; forming an offset oxide on the preliminary stack structure; measuring thickness data of the offset oxide; and scanning the offset oxide using a reactive gas cluster ion beam. The scanning the offset oxide includes setting a scan speed based on the measured thickness data of the offset oxide, and forming a gas cluster.

摘要翻译： 根据本发明构思的示例性实施例，制造半导体器件的方法包括：形成初步叠层结构，所述预备叠层结构限定通孔; 在通孔中形成保护层和电介质层; 在通孔中形成通道图案，间隙填充图案和接触图案; 在预备堆叠结构上形成偏移氧化物; 测量偏移氧化物的厚度数据; 并使用反应性气体簇离子束扫描偏移氧化物。 扫描偏移氧化物包括基于测量的偏移氧化物的厚度数据设置扫描速度，并形成气体簇。

公开(公告)号：US09082659B1

公开(公告)日：2015-07-14

申请号：US14643527

申请日：2015-03-10

申请人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

发明人： Phil-Ouk Nam ,  Jun-Kyu Yang ,  Byong-Hyun Jang ,  Ki-Hyun Hwang ,  Jae-Young Ahn

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7889 ,  H01L29/7926

摘要： A vertical type semiconductor device can include a vertical pillar structure that includes a channel pattern with an outer wall. Horizontal insulating structures can be vertically spaced apart from one another along the vertical pillar structure to define first vertical gaps therebetween at first locations away from the outer wall and to define second vertical gaps therebetween at the outer wall, where the second vertical gaps are wider than the first vertical gaps. Horizontal wordline structures can be conformally located in the first and second vertical gaps between the vertically spaced apart horizontal insulating structures, so that the horizontal wordline structures can be vertically thinner across the first vertical gaps than across the second vertical gaps.

摘要翻译： 垂直型半导体器件可以包括垂直柱结构，其包括具有外壁的沟道图案。 水平绝缘结构可以沿着垂直柱结构彼此垂直间隔开，以在远离外壁的第一位置处限定第一垂直间隙，并且在外壁处限定第二垂直间隙，其中第二垂直间隙宽于 第一垂直间隙。 水平字线结构可以共形地位于垂直间隔开的水平绝缘结构之间的第一和第二垂直间隙中，使得水平字线结构可跨越第一垂直间隙而横跨第二垂直间隙。

公开(公告)号：US09064736B2

公开(公告)日：2015-06-23

申请号：US14248003

申请日：2014-04-08

申请人： Joon-Suk Lee ,  Woong Lee ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang

发明人： Joon-Suk Lee ,  Woong Lee ,  Hun-Hyeong Lim ,  Ki-Hyun Hwang

IPC分类号： H01L21/311 ,  H01L27/115

CPC分类号： H01L27/11578 ,  H01L27/1157 ,  H01L27/11582

摘要： A method of manufacturing a three-dimensional semiconductor memory device is provided. The method includes alternately stacking a first insulation film, a first sacrificial film, alternating second insulation films and second sacrificial films, a third sacrificial film and a third insulation film on a substrate. A channel hole is formed to expose a portion of the substrate while passing through the first insulation film, the first sacrificial film, the second insulation films, the second sacrificial films, the third sacrificial film and the third insulation film. The method further includes forming a semiconductor pattern on the portion of the substrate exposed in the channel hole by epitaxial growth. Forming the semiconductor pattern includes forming a lower epitaxial film, doping an impurity into the lower epitaxial film, and forming an upper epitaxial film on the lower epitaxial film. Forming the lower epitaxial film, doping the impurity into the lower epitaxial film and forming the upper epitaxial film are all performed in-situ, and the semiconductor pattern includes a doped region and an undoped region.

摘要翻译： 提供一种制造三维半导体存储器件的方法。 该方法包括在基板上交替堆叠第一绝缘膜，第一牺牲膜，交替的第二绝缘膜和第二牺牲膜，第三牺牲膜和第三绝缘膜。 形成通道孔，以在穿过第一绝缘膜，第一牺牲膜，第二绝缘膜，第二牺牲膜，第三牺牲膜和第三绝缘膜的同时暴露衬底的一部分。 该方法还包括通过外延生长在暴露在通道孔中的衬底的部分上形成半导体图案。 形成半导体图案包括形成下部外延膜，将杂质掺杂到下部外延膜中，以及在下部外延膜上形成上部外延膜。 形成下部外延膜，将杂质掺杂到下部外延膜中并形成上部外延膜全部原位进行，并且半导体图案包括掺杂区域和未掺杂区域。

公开(公告)号：US20140084357A1

公开(公告)日：2014-03-27

申请号：US13949447

申请日：2013-07-24

申请人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

发明人： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

摘要： A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

摘要翻译： 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅极电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。

公开(公告)号：US20110165750A1

公开(公告)日：2011-07-07

申请号：US12984940

申请日：2011-01-05

申请人： Jun-Kyu Yang ,  Young-Geun Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Chan-Jin Park

发明人： Jun-Kyu Yang ,  Young-Geun Park ,  Ki-Hyun Hwang ,  Han-Mei Choi ,  Chan-Jin Park

IPC分类号： H01L21/336

CPC分类号： H01L21/7682 ,  H01L21/02164 ,  H01L21/02266 ,  H01L23/5222 ,  H01L2924/0002 ,  H01L2924/00

摘要： In methods of manufacturing a semiconductor device, a plurality of gate structures spaced apart from each other and oxide layer patterns. A sputtering process using the oxide layer patterns as a sputtering target to connect the oxide layer patterns on the adjacent gate structures to each other is performed, so that a gap is formed between the gate structures. A volume of the gap is formed uniformly to have desired volume by controlling a thickness of the oxide layer patterns.

摘要翻译： 在制造半导体器件的方法中，多个彼此间隔开的栅极结构和氧化物层图案。 执行使用氧化物层图案作为溅射靶的溅射工艺来将相邻栅极结构上的氧化物层图案彼此连接，使得在栅极结构之间形成间隙。 通过控制氧化物层图案的厚度，使间隙的体积均匀地形成为具有期望的体积。