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    Semiconductor memory device and method of manufacturing the same
    1.
    发明授权
    Semiconductor memory device and method of manufacturing the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US09530899B2

    公开(公告)日：2016-12-27

    申请号：US14474942

    申请日：2014-09-02

    Applicant: Bi O Kim ,  Jin-Tae Noh ,  Su-Jin Shin ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    Inventor： Bi O Kim ,  Jin-Tae Noh ,  Su-Jin Shin ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    IPC: H01L29/792 ,  H01L27/115 ,  G11C16/04 ,  H01L21/28 ,  H01L29/66

    CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833

    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括交替层叠在基板上的绝缘层和栅极电极，垂直通过绝缘层和栅电极的垂直沟道，以及设置在垂直线之间的阈值电压控制绝缘层，隧道绝缘层和电荷存储层 沟道和栅电极，其中所述阈值电压控制绝缘层设置在所述电荷存储层和所述垂直沟道之间，并且包括被配置为抑制在所述垂直沟道中形成反型层的材料。

    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20150129954A1

    公开(公告)日：2015-05-14

    申请号：US14474942

    申请日：2014-09-02

    Applicant: Bi O. Kim ,  Jin-Tae Noh ,  Su-Jin Shin ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    Inventor： Bi O. Kim ,  Jin-Tae Noh ,  Su-Jin Shin ,  Jae-Young Ahn ,  Ki-Hyun Hwang

    IPC: H01L29/792

    CPC classification number: H01L29/7926 ,  H01L21/28282 ,  H01L27/11582 ,  H01L29/66833

    Abstract: A semiconductor device and a method of manufacturing the same are provided. The semiconductor device includes insulation layers and gate electrodes alternately stacked on a substrate, a vertical channel vertically passing through the insulation layers and the gate electrodes, and a threshold voltage controlling insulation layer, a tunnel insulation layer and a charge storage layer disposed between the vertical channel and the gate electrodes, wherein the threshold voltage controlling insulation layer is disposed between the charge storage layer and the vertical channel and including a material configured to suppress an inversion layer from being formed in the vertical channel.

    Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括交替层叠在基板上的绝缘层和栅极电极，垂直通过绝缘层和栅电极的垂直沟道，以及设置在垂直线之间的阈值电压控制绝缘层，隧道绝缘层和电荷存储层 沟道和栅电极，其中所述阈值电压控制绝缘层设置在所述电荷存储层和所述垂直沟道之间，并且包括被配置为抑制在所述垂直沟道中形成反型层的材料。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20160133643A1

    公开(公告)日：2016-05-12

    申请号：US14995586

    申请日：2016-01-14

    Applicant: Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

    Inventor： Ji-Hoon Choi ,  Dong-Kyum Kim ,  Jin-Gyun Kim ,  Su-Jin Shin ,  Sang-Hoon Lee ,  Ki-Hyun Hwang

    IPC: H01L27/115 ,  H01L21/28 ,  H01L21/02

    CPC classification number: H01L27/11582 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02236 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28008 ,  H01L21/28282 ,  H01L27/1157 ,  H01L29/7926

    Abstract: A semiconductor device is provided. The semiconductor includes a plurality of interlayer insulating layers and a plurality of gate electrodes alternately stacked in a first direction on a substrate. The plurality of interlayer insulating layers and the plurality of gate electrodes constitute a side surface extended in the first direction. A gate dielectric layer is disposed on the side surface. A channel pattern is disposed on the gate dielectric layer. The gate dielectric layer includes a protective pattern, a charge trap layer, and a tunneling layer. The protective pattern includes a portion disposed on a corresponding gate electrode of the plurality of gate electrodes. The charge trap layer is disposed on the protective pattern. The tunneling layer is disposed between the charge trap layer and the channel pattern. The protective pattern is denser than the charge trap layer.

    Abstract translation: 提供半导体器件。 半导体包括在基板上沿第一方向交替堆叠的多个层间绝缘层和多个栅电极。 多个层间绝缘层和多个栅电极构成在第一方向上延伸的侧面。 栅电介质层设置在侧表面上。 沟道图案设置在栅介质层上。 栅介质层包括保护图案，电荷陷阱层和隧穿层。 保护图案包括设置在多个栅电极的对应的栅电极上的部分。 电荷陷阱层设置在保护图案上。 隧道层设置在电荷陷阱层和沟道图案之间。 保护图案比电荷陷阱层更致密。

    VERTICAL MEMORY DEVICES
    7.
    发明申请
    VERTICAL MEMORY DEVICES 审中-公开
    垂直存储器件

    公开(公告)号：US20150145014A1

    公开(公告)日：2015-05-28

    申请号：US14471778

    申请日：2014-08-28

    Applicant: Su-Jin SHIN ,  Dong-Chul YOO ,  Ki-Hyun HWANG

    Inventor： Su-Jin SHIN ,  Dong-Chul YOO ,  Ki-Hyun HWANG

    IPC: H01L27/115 ,  H01L29/792 ,  H01L29/51 ,  H01L29/788

    CPC classification number: H01L27/11563 ,  H01L27/11517 ,  H01L27/11582 ,  H01L29/511 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7889 ,  H01L29/7926

    Abstract: A vertical memory device includes a substrate, a first cell block and a second cell block. The substrate includes a central region and a peripheral region. At least one first cell block is on the central region. The first cell block includes a first channel and first gate lines. At least one second cell block is on the peripheral region. The second cell block includes a second channel and second gate lines. The second cell block has a width greater than a width of the first cell block. The first and second channel extend in a first direction vertical to a top surface of the substrate. The first gate lines surround the first channel and the first gate lines are spaced apart from each other in the first direction. The second gate lines surround the second channel and are spaced apart from each other in the first direction.

    Abstract translation: 垂直存储器件包括衬底，第一电池块和第二电池块。 基板包括中心区域和周边区域。 至少一个第一细胞块位于中心区域。 第一单元块包括第一通道和第一栅极线。 至少一个第二单元块位于外围区域上。 第二单元块包括第二通道和第二栅极线。 第二单元块的宽度大于第一单元块的宽度。 第一和第二通道在垂直于衬底顶表面的第一方向上延伸。 第一栅极线围绕第一沟道并且第一栅极线在第一方向上彼此间隔开。 第二栅极线围绕第二通道并且在第一方向上彼此间隔开。

    NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME
    9.
    发明申请
    NON-VOLATILE MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
    非易失性存储器件及其制造方法

    公开(公告)号：US20140080298A1

    公开(公告)日：2014-03-20

    申请号：US14080877

    申请日：2013-11-15

    Applicant: Jung-Geun JEE ,  Seok-Hoon KIM ,  Su-Jin SHIN ,  Woo-Sung LEE ,  Tae-Ouk KWON

    Inventor： Jung-Geun JEE ,  Seok-Hoon KIM ,  Su-Jin SHIN ,  Woo-Sung LEE ,  Tae-Ouk KWON

    IPC: H01L21/285 ,  H01L21/28

    CPC classification number: H01L27/11558 ,  H01L21/2807 ,  H01L21/28556 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66825 ,  H01L29/7881

    Abstract: A non-volatile memory device includes a field region that defines an active region in a semiconductor substrate, a floating gate pattern on the active region, a dielectric layer on the floating gate pattern and a control gate on the dielectric layer. The control gate includes a first conductive pattern that has a first composition that crystallizes in a first temperature range, and a second conductive pattern that has a second composition that is different from the first composition and that crystallizes in a second temperature range that is lower than the first temperature range, the first conductive pattern being between the dielectric layer and the second conductive pattern.

    Abstract translation: 非易失性存储器件包括限定半导体衬底中的有源区域的场区域，有源区域上的浮置栅极图案，浮置栅极图案上的介电层和介电层上的控制栅极。 控制栅极包括具有在第一温度范围内结晶的第一组成的第一导电图案和具有与第一组成不同的第二组成的第二导电图案，并且在低于第一组成的第二温度范围内结晶 第一温度范围，第一导电图案在介电层和第二导电图案之间。

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