公开(公告)号：US06700153B2

公开(公告)日：2004-03-02

申请号：US10136385

申请日：2002-05-02

申请人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

发明人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

IPC分类号： H01L27108

CPC分类号： H01L28/91 ,  H01L27/10855 ,  Y10T29/5111

摘要： An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

公开(公告)号：US06911364B2

公开(公告)日：2005-06-28

申请号：US10687838

申请日：2003-10-20

申请人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

发明人： Jung-Hwan Oh ,  Ki-Hyun Hwang ,  Jae-Young Park ,  In-Seak Hwang ,  Young-Wook Park

IPC分类号： H01L21/02 ,  H01L21/8242

CPC分类号： H01L28/91 ,  H01L27/10855

摘要： An etch stop layer is formed over a surface of an interlayer insulating layer and over a surface of a conductive plug extending at a depth from the surface of the interlayer insulating layer. A lower mold layer is deposited over the etch stop layer, and a wet etch rate of the lower mold layer is adjusted by adding dopants to the lower mold layer during formation of the lower mold layer, and by annealing the lower mold layer. An upper mold layer is then deposited over the surface of the lower mold layer, such that a wet etch rate of the upper mold layer is less than the adjusted wet etch rate of the lower mold layer. The upper mold layer, the lower mold layer and the etch stop layer are then subjected to dry etching to form an opening therein which exposes at least a portion of the surface of the contact plug. Then a wet etching of the upper mold layer and the lower mold layer is performed so as to increase a size of the opening at the lower mold layer and so at to expose a surface portion of the etch stop layer adjacent the surface of the conductive plug. A conductive material is then deposited over the surface of the opening in the upper and lower mold layers to define a capacitor electrode.

摘要翻译： 在层间绝缘层的表面上方和在从层间绝缘层的表面的深度延伸的导电插塞的表面之上形成蚀刻停止层。 在蚀刻停止层上沉积下模层，并且通过在形成下模层期间向下模层添加掺杂剂并且通过对下模层进行退火来调节下模层的湿蚀刻速率。 然后将上模层沉积在下模层的表面上，使得上模层的湿蚀刻速率小于下模层的经调整的湿蚀刻速率。 然后对上模层，下模层和蚀刻停止层进行干蚀刻以在其中形成露出接触塞表面的至少一部分的开口。 然后进行上模层和下模层的湿式蚀刻，以便增加下模层上开口的尺寸，从而暴露出邻近导电塞表面的蚀刻停止层的表面部分 。 然后将导电材料沉积在上模具层和下模层中的开口的表面上，以限定电容器电极。

公开(公告)号：US07498213B2

公开(公告)日：2009-03-03

申请号：US11530218

申请日：2006-09-08

申请人： Won-Jin Kim ,  Young-Wook Park ,  Jeong-Do Ryu

发明人： Won-Jin Kim ,  Young-Wook Park ,  Jeong-Do Ryu

IPC分类号： H01L21/338 ,  H01L21/336

CPC分类号： H01L21/0209 ,  H01L21/302 ,  H01L21/6708 ,  H01L21/76895 ,  H01L27/10844 ,  H01L27/10882 ,  H01L29/7842

摘要： Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate. The at least one layer can be removed on the second side of the semiconductor substrate, while the capping layer and the pattern of the at least one layer is maintained on the first side of the semiconductor substrate. A portion of the capping layer can be removed on the first side of the semiconductor substrate.

摘要翻译： 制造半导体器件的方法可以包括在半导体衬底的第一和第二侧上形成至少一个层。 可以在半导体衬底的第一侧上去除至少一个层的部分，以在衬底的第一侧上形成至少一层的图案，同时将至少一层保持在衬底的第二面上 。 可以在衬底的第一侧上的至少一层的图案和半导体衬底的第二侧上的至少一个层上形成覆盖层。 可以在半导体衬底的第二侧上去除覆盖层，从而在衬底的第二侧上保持覆盖层的同时暴露衬底的第二面上的至少一个层。 可以在半导体衬底的第二侧上移除至少一个层，同时覆盖层和至少一层的图案保持在半导体衬底的第一侧上。 可以在半导体衬底的第一侧上去除覆盖层的一部分。

公开(公告)号：US07201807B2

公开(公告)日：2007-04-10

申请号：US10734479

申请日：2003-12-12

申请人： Eun-Taek Yim ,  Young-Wook Park ,  In-Sung Park ,  Han-Mei Choi ,  Kyoung-Seok Kim

发明人： Eun-Taek Yim ,  Young-Wook Park ,  In-Sung Park ,  Han-Mei Choi ,  Kyoung-Seok Kim

IPC分类号： B08B5/00 ,  B08B9/093

CPC分类号： C23C16/4405 ,  B08B7/00 ,  B08B7/0035 ,  H01J37/32862 ,  H01L21/3162 ,  Y10S438/905

摘要： Disclosed are a method for cleaning a deposition chamber by removing attached metal oxides, and a deposition apparatus for performing in situ cleaning. A first gas and a second gas are provided into the deposition chamber. The first gas is reacted with metal included in the metal oxide to generate reacting residues. The second gas then decomposes the reacting residues, and the decomposed residues are exhausted out of the chamber. Thus, this cleaning process can be rapidly accomplished while the deposition chamber is not opened or separated from a deposition apparatus.

摘要翻译： 公开了通过去除附着的金属氧化物来清洁沉积室的方法，以及用于进行原位清洁的沉积装置。 第一气体和第二气体被提供到沉积室中。 第一种气体与包含在金属氧化物中的金属反应以产生反应残余物。 然后第二气体分解反应残余物，并将分解的残余物排出室外。 因此，当沉积室不从沉积设备打开或分离时，可以快速实现该清洁过程。

公开(公告)号：US20070004211A1

公开(公告)日：2007-01-04

申请号：US11530218

申请日：2006-09-08

申请人： Won Kim ,  Young-Wook Park ,  Jeong-Do Ryu

发明人： Won Kim ,  Young-Wook Park ,  Jeong-Do Ryu

IPC分类号： H01L21/461 ,  H01L21/302

CPC分类号： H01L21/0209 ,  H01L21/302 ,  H01L21/6708 ,  H01L21/76895 ,  H01L27/10844 ,  H01L27/10882 ,  H01L29/7842

摘要： Methods of fabricating a semiconductor device can include forming at least one layer on a first and a second side of a semiconductor substrate. Portions of the at least one layer may be removed on the first side of the semiconductor substrate to form a pattern of the at least one layer on the first side of the substrate while the at least one layer is maintained on the second side of the substrate. A capping layer can be formed on the pattern of the at least one layer on the first side of the substrate and on the at least one layer on the second side of the semiconductor substrate. The capping layer can be removed on the second side of the semiconductor substrate, thereby exposing the at least one layer on the second side of the substrate while maintaining the capping layer on the first side of the substrate. The at least one layer can be removed on the second side of the semiconductor substrate, while the capping layer and the pattern of the at least one layer is maintained on the first side of the semiconductor substrate. A portion of the capping layer can be removed on the first side of the semiconductor substrate.

摘要翻译： 制造半导体器件的方法可以包括在半导体衬底的第一和第二侧上形成至少一个层。 可以在半导体衬底的第一侧上去除至少一个层的部分，以在衬底的第一侧上形成至少一层的图案，同时将至少一层保持在衬底的第二面上 。 可以在衬底的第一侧上的至少一层的图案和半导体衬底的第二侧上的至少一个层上形成覆盖层。 可以在半导体衬底的第二侧上去除覆盖层，从而在衬底的第二侧上保持覆盖层的同时暴露衬底的第二面上的至少一个层。 可以在半导体衬底的第二侧上移除至少一个层，同时覆盖层和至少一层的图案保持在半导体衬底的第一侧上。 可以在半导体衬底的第一侧上去除覆盖层的一部分。

公开(公告)号：US20060128127A1

公开(公告)日：2006-06-15

申请号：US11290648

申请日：2005-12-01

申请人： Jung-Hun Seo ,  Young-Wook Park ,  Jin-Gi Hong ,  Kyung-Bum Koo ,  Eun-Taeck Lee

发明人： Jung-Hun Seo ,  Young-Wook Park ,  Jin-Gi Hong ,  Kyung-Bum Koo ,  Eun-Taeck Lee

IPC分类号： H01L21/20

CPC分类号： H01L21/28562 ,  C23C16/34 ,  C23C16/45523 ,  C23C16/45561 ,  C23C16/45565 ,  C23C16/45574

摘要： In a method and an apparatus for depositing a metal compound layer, a first source gas and a second source gas may be provided onto a substrate to deposit a first metal compound layer on the substrate. The first source gas may include a metal and halogen elements, and the second source gas may include a first material capable of being reacted with the metal and a second material capable of being reacted with the halogen element. The first and the second source gases may be provided at a first flow rate ratio. A second metal compound layer may be deposited on the first metal compound layer by providing the first and the second source gases with a second flow rate ratio different from the first flow rate ratio. The apparatus may include a process chamber configured to receive a substrate, a gas supply system, and a flow rate control device.

摘要翻译： 在用于沉积金属化合物层的方法和装置中，可以将第一源气体和第二源气体提供到衬底上以在衬底上沉积第一金属化合物层。 第一源气体可以包括金属和卤素元素，并且第二源气体可以包括能够与金属反应的第一材料和能够与卤素元素反应的第二材料。 第一和第二源气体可以以第一流量比提供。 可以通过使第一和第二源气体具有与第一流量比不同的第二流量比，将第二金属化合物层沉积在第一金属化合物层上。 该装置可以包括被配置为接收基板，气体供应系统和流量控制装置的处理室。

公开(公告)号：US06989338B2

公开(公告)日：2006-01-24

申请号：US10737394

申请日：2003-12-15

申请人： Han-Mei Choi ,  Young-Wook Park ,  Eun-Taek Yim ,  Dong-Jo Kang ,  Kyoung-Seok Kim

发明人： Han-Mei Choi ,  Young-Wook Park ,  Eun-Taek Yim ,  Dong-Jo Kang ,  Kyoung-Seok Kim

IPC分类号： H01L21/26

CPC分类号： H01L21/28194 ,  H01L29/513 ,  H01L29/517

摘要： Disclosed is a method for forming a multi-layered structure having at least two films on a semiconductor substrate. The substrate is disposed on a thermally conductible stage for supporting the substrate. After the distance between the stage and the substrate is adjusted to a first interval so that the substrate has a first temperature by heat transferred from the stage, a first thin film is formed on the substrate at the first temperature. The distance is then adjusted from the first interval to a second interval so that the substrate reaches a second temperature, and then a second thin film is formed on the first thin film at the second temperature, thereby forming the multi-layered structure on the substrate. The multi-layered structure can be employed for a gate insulation film or the dielectric film of a capacitor.

摘要翻译： 公开了一种在半导体衬底上形成至少具有两个膜的多层结构的方法。 基板设置在用于支撑基板的导热性台上。 在阶段和衬底之间的距离被调整到第一间隔，使得衬底具有通过从载物台传递的热量的第一温度，在第一温度下在衬底上形成第一薄膜。 然后将距离从第一间隔调整到第二间隔，使得衬底达到第二温度，然后在第二温度下在第一薄膜上形成第二薄膜，从而在衬底上形成多层结构 。 多层结构可以用于栅极绝缘膜或电容器的电介质膜。

公开(公告)号：US20050054189A9

公开(公告)日：2005-03-10

申请号：US10706647

申请日：2003-11-12

申请人： Hyoung-Joon Kim ,  Young-Wook Park ,  Byeong-Yun Nam

发明人： Hyoung-Joon Kim ,  Young-Wook Park ,  Byeong-Yun Nam

IPC分类号： H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L21/336 ,  H01L21/4763

CPC分类号： H01L21/76831 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

摘要： The present invention provides methods of fabricating integrated circuit devices that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

摘要翻译： 本发明提供制造集成电路器件的方法，该器件包括微电子衬底和设置在微电子衬底上的导电层。 绝缘层设置在导电层上，绝缘层包括延伸超过导电层的伸出部分。 侧壁绝缘区域横向地布置在导电层的侧壁附近并且在绝缘层的悬垂部分和微电子衬底之间延伸。

公开(公告)号：US06680511B2

公开(公告)日：2004-01-20

申请号：US10052721

申请日：2002-01-18

申请人： Hyoung-Joon Kim ,  Young-Wook Park ,  Byeong-Yun Nam

发明人： Hyoung-Joon Kim ,  Young-Wook Park ,  Byeong-Yun Nam

IPC分类号： H01L2976

CPC分类号： H01L21/76831 ,  H01L21/76885 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885

摘要： The present invention provide integrated circuit devices and methods of fabricating the same that include a microelectronic substrate and a conductive layer disposed on the microelectronic substrate. An insulating layer is disposed on the conductive layer and the insulating layer includes an overhanging portion that extends beyond the conductive layer. A sidewall insulating region is disposed laterally adjacent to a sidewall of the conductive layer and extends between the overhanging portion of the insulating layer and the microelectronic substrate.

摘要翻译： 本发明提供集成电路器件及其制造方法，其包括微电子衬底和设置在微电子衬底上的导电层。 绝缘层设置在导电层上，绝缘层包括延伸超过导电层的伸出部分。 侧壁绝缘区域横向地布置在导电层的侧壁附近并且在绝缘层的悬垂部分和微电子衬底之间延伸。

公开(公告)号：US08039054B2

公开(公告)日：2011-10-18

申请号：US10854942

申请日：2004-05-27

申请人： In-Sung Park ,  Young-Wook Park ,  Myeong-Jin Kim ,  Eun-Taek Yim ,  Han-Mei Choi ,  Kyoung-Seok Kim ,  Beung-Keun Lee

发明人： In-Sung Park ,  Young-Wook Park ,  Myeong-Jin Kim ,  Eun-Taek Yim ,  Han-Mei Choi ,  Kyoung-Seok Kim ,  Beung-Keun Lee

IPC分类号： C23C16/00

CPC分类号： C23C16/45531 ,  C23C16/403 ,  C23C16/45527 ,  C23C16/45561

摘要： A layer deposition method includes: feeding a reactant with a first flow of an inert gas as a carrier gas into a reaction chamber to chemisorb the reactant on a substrate; feeding the first flow of the inert gas to purge the reaction chamber and a first reactant feed line; and feeding the second flow of the inert gas into the reaction chamber through a feed line different from the first reactant feed line.

摘要翻译： 层沉积方法包括：将具有作为载气的惰性气体的第一流的反应物进料到反应室中以化学吸附基材上的反应物; 供给惰性气体的第一流以吹扫反应室和第一反应物进料管线; 以及通过不同于第一反应物进料管线的进料管线将惰性气体的第二流量进料到反应室中。