公开(公告)号：US08637407B2

公开(公告)日：2014-01-28

申请号：US13242504

申请日：2011-09-23

申请人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

发明人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： G11C16/0483 ,  G11C5/06 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

公开(公告)号：US08541306B2

公开(公告)日：2013-09-24

申请号：US12983478

申请日：2011-01-03

申请人： Song-yi Yang ,  Seung-pil Chung ,  Dong-hyun Kim ,  O-ik Kwon ,  Hong Cho

发明人： Song-yi Yang ,  Seung-pil Chung ,  Dong-hyun Kim ,  O-ik Kwon ,  Hong Cho

IPC分类号： H01L23/52 ,  H01L21/302 ,  H01L21/768

CPC分类号： H01L27/11519 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.

摘要翻译： 公开了一种在半导体器件上形成图案的半导体器件和方法。 半导体器件可以包括具有最小尺寸的高密度图案，其可以小于光刻工艺的分辨率极限，并且可以具有包括存储单元区域和相邻连接区域的基板，从第一导电线延伸的多个第一导电线 存储单元区域连接到第一方向上的连接区域;多个第二导线，其从相应的第一导线连接到宽度等于每个第一导电线宽度的两倍的多个焊盘。 该方法可以包括两个级别的间隔物形成以提供子分辨率线宽度和空间以及最小线宽和空间的选定倍数。

公开(公告)号：US20120049377A1

公开(公告)日：2012-03-01

申请号：US12983478

申请日：2011-01-03

申请人： Song-Yi Yang ,  Seung-pil Chung ,  Dong-hyun Kim ,  O-ik Kwon ,  Hong Cho

发明人： Song-Yi Yang ,  Seung-pil Chung ,  Dong-hyun Kim ,  O-ik Kwon ,  Hong Cho

IPC分类号： H01L23/52 ,  H01L21/302 ,  H01L21/768

CPC分类号： H01L27/11519 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of forming patterns on a semiconductor device are disclosed. The semiconductor device may include high-density patterns with a minimum size that may be less the resolution limit of a photolithography process, and may have a substrate including a memory cell region and an adjacent connection region, a plurality of first conductive lines extending from the memory cell region to the connection region in a first direction, a plurality of second conductive lines connected from respective first conductive lines to a plurality of pads having a width equal to twice the width of each of the first conductive lines. The method may include two levels of spacer formation to provide sub resolution line widths and spaces as well as selected multiples of the minimum line widths and spaces.

摘要翻译： 公开了一种在半导体器件上形成图案的半导体器件和方法。 半导体器件可以包括具有最小尺寸的高密度图案，其可以小于光刻工艺的分辨率极限，并且可以具有包括存储单元区域和相邻连接区域的基板，从第一导电线延伸的多个第一导电线 存储单元区域连接到第一方向上的连接区域;多个第二导线，其从相应的第一导线连接到宽度等于每个第一导电线宽度的两倍的多个焊盘。 该方法可以包括两个级别的间隔物形成以提供子分辨率线宽度和空间以及最小线宽和空间的选定倍数。

公开(公告)号：US06872258B2

公开(公告)日：2005-03-29

申请号：US10178757

申请日：2002-06-25

申请人： Jong-chul Park ,  Dong-hyun Kim ,  O-ik Kwon ,  Hye-jin Jo

发明人： Jong-chul Park ,  Dong-hyun Kim ,  O-ik Kwon ,  Hye-jin Jo

IPC分类号： H01L21/3065 ,  C23C16/44 ,  C23C16/455 ,  H01L21/00 ,  C23C16/00 ,  C23F1/00 ,  H01L21/306

CPC分类号： C23C16/45565 ,  C23C16/45589 ,  H01L21/67017

摘要： A shower head for adjusting distribution of a reactant gas in a process region of a semiconductor manufacturing reaction chamber, wherein a top plate has a gas port for introducing the reactant gas into the reaction chamber; a face plate, having through holes, disposed opposite the process region; a first baffle plate, having through holes, disposed between the top plate and the face plate and capable of moving up or down, wherein the first baffle plate has a top surface that defines a first gap for forming a first lateral flow passage; a second baffle plate, having through holes, disposed between the first baffle plate and the face plate and capable of moving up or down, wherein the second baffle plate has a top surface that defines a second gap for forming a second lateral flow passage; and a gap controller for determining widths of the first and second gaps.

公开(公告)号：US20170133399A1

公开(公告)日：2017-05-11

申请号：US15222374

申请日：2016-07-28

申请人： Ki Jeong KIM ,  Byoung Jun CHOI ,  O Ik KWON

发明人： Ki Jeong KIM ,  Byoung Jun CHOI ,  O Ik KWON

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L23/535 ,  H01L29/792

CPC分类号： H01L27/11582 ,  H01L23/535 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/66833 ,  H01L29/7926

摘要： A memory device includes gate electrode layers stacked on top of each other on a substrate, a channel region on a cell region of the substrate and extending through the gate electrode layers in a direction perpendicular to an upper surface of the substrate, cell contacts connected to the gate electrode layers, an active region on a peripheral circuit region of the substrate, planar gate electrode layers on the peripheral circuit region and adjacent to the active region, a cover layer on the active region, and peripheral contacts connected to the active region and the planar gate electrode layers. At least a portion of the peripheral contacts are separated from the cover layer above the planar gate electrode layers.

公开(公告)号：US20140106567A1

公开(公告)日：2014-04-17

申请号：US14133296

申请日：2013-12-18

申请人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-Chan Kim ,  Myeong-Cheol Kim

发明人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-Chan Kim ,  Myeong-Cheol Kim

IPC分类号： H01L27/115

CPC分类号： G11C16/0483 ,  G11C5/06 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Methods of forming a semiconductor device may include providing a feature layer having a first region and a second region. The methods may also include forming a dual mask layer on the feature layer. The methods may further include forming a variable mask layer on the dual mask layer. The methods may additionally include forming a first structure on the feature layer in the first region and a second structure on the feature layer in the second region by patterning the variable mask layer and the dual mask layer. The methods may also include forming a first spacer on a sidewall of the first structure and a second spacer on a sidewall of the second structure. The methods may further include removing the first structure while maintaining at least a portion of the second structure.

公开(公告)号：US20130134496A1

公开(公告)日：2013-05-30

申请号：US13599233

申请日：2012-08-30

申请人： Sung-Soo AHN ,  O IK KWON ,  Bum-Soo KIM ,  Hyun-Sung KIM ,  Kyoung-Sub SHIN ,  Min-Kyung YUN ,  Seung-Pil CHUNG ,  Won-Bong JUNG

发明人： Sung-Soo AHN ,  O IK KWON ,  Bum-Soo KIM ,  Hyun-Sung KIM ,  Kyoung-Sub SHIN ,  Min-Kyung YUN ,  Seung-Pil CHUNG ,  Won-Bong JUNG

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L29/7883 ,  H01L21/7682 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/42364 ,  H01L29/66825 ,  H01L29/7881

摘要： A method of manufacturing a semiconductor device, the method including forming a tunnel insulating layer on an upper surface of a substrate, forming gate patterns on an upper surface of the tunnel insulating layer, forming capping layer patterns on sidewalls of the gate patterns and on the upper surface of the tunnel insulating layer, etching a portion of the tunnel insulating layer that is not covered with the gate patterns or the capping layer patterns to form a tunnel insulating layer pattern, and forming a first insulating layer on the upper surface of the substrate to cover the gate patterns, the capping layer patterns, and the tunnel insulating layer pattern, wherein the first insulating layer has an air gap between the capping layer patterns.

摘要翻译： 一种制造半导体器件的方法，所述方法包括在衬底的上表面上形成隧道绝缘层，在隧道绝缘层的上表面上形成栅极图案，在栅极图案的侧壁上形成覆盖层图案，并且在 隧道绝缘层的上表面，蚀刻未被栅极图案或覆盖层图案覆盖的隧道绝缘层的一部分以形成隧道绝缘层图案，并且在衬底的上表面上形成第一绝缘层 以覆盖栅极图案，覆盖层图案和隧道绝缘层图案，其中第一绝缘层在封盖层图案之间具有气隙。

公开(公告)号：US08110506B2

公开(公告)日：2012-02-07

申请号：US12428963

申请日：2009-04-23

申请人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

发明人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

IPC分类号： H01L21/302 ,  H01L21/461

CPC分类号： G11C16/0483 ,  G11C5/06 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

摘要翻译： 可以通过使用自对准反向图案化来同时形成多个掩模图案来提供形成半导体器件的方法，包括具有不同宽度的各个掩模图案元件。

公开(公告)号：US20050196921A1

公开(公告)日：2005-09-08

申请号：US11033447

申请日：2005-01-12

申请人： Yong-Woo Lee ,  Jong-Chul Park ,  O-Ik Kwon ,  Sang-Sup Jeong

发明人： Yong-Woo Lee ,  Jong-Chul Park ,  O-Ik Kwon ,  Sang-Sup Jeong

IPC分类号： H01L21/28 ,  H01L21/3205 ,  H01L21/4763 ,  H01L21/8242

CPC分类号： H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

摘要： A method of forming a contact for a semiconductor device by forming a storage node contact in a semiconductor substrate having a first pad and a second pad formed thereon. The storage node contact is connected to the second pad. A bit line electrically insulated from the storage node contact by a spacer and electrically connected to the first pad.

摘要翻译： 一种通过在其上形成有第一焊盘和第二焊盘的半导体衬底中形成存储节点接触来形成半导体器件的接触的方法。 存储节点触点连接到第二焊盘。 与存储节点接触的位线通过间隔物电绝缘并电连接到第一焊盘。

公开(公告)号：US20100055914A1

公开(公告)日：2010-03-04

申请号：US12428963

申请日：2009-04-23

申请人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

发明人： Jae-Ho Min ,  O-Ik Kwon ,  Bum-Soo Kim ,  Dong-chan Kim ,  Myeong-cheol Kim

IPC分类号： H01L21/308

CPC分类号： G11C16/0483 ,  G11C5/06 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/32139 ,  H01L27/0207 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11531 ,  H01L27/11548 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

摘要： Methods of forming a semiconductor device can be provided by simultaneously forming a plurality of mask patterns using self-aligned reverse patterning, including respective mask pattern elements having different widths.

摘要翻译： 可以通过使用自对准反向图案化来同时形成多个掩模图案来提供形成半导体器件的方法，包括具有不同宽度的各个掩模图案元件。