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    Nonvolatile memory device with 3D memory cell array
    1.
    发明授权
    Nonvolatile memory device with 3D memory cell array 有权
    具有3D存储单元阵列的非易失性存储器件

    公开(公告)号：US08570808B2

    公开(公告)日：2013-10-29

    申请号：US13186987

    申请日：2011-07-20

    申请人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    发明人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    IPC分类号： G11C16/04

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

    摘要： A nonvolatile memory device includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

    摘要翻译： 非易失性存储器件包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压信号的电压发生器电路，以及 行选择电路，其将所述第一电压信号同时施加到所选择的字线，并将所述第二电压信号施加到未选择的字线。 所选择的字线和未选字线具有不同的电阻，而第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

    NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY
    2.
    发明申请
    NONVOLATILE MEMORY DEVICE WITH 3D MEMORY CELL ARRAY 有权
    具有3D存储单元阵列的非易失性存储器件

    公开(公告)号：US20120033501A1

    公开(公告)日：2012-02-09

    申请号：US13186987

    申请日：2011-07-20

    申请人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    发明人： Jung-hoon Park ,  Kyung-Hwa Kang ,  Chi-Weon Yoon ,  Sang-Wan Nam ,  Sung-Won Yun

    IPC分类号： G11C16/10 ,  G11C16/04

    CPC分类号： G11C11/5642 ,  G11C16/0483 ,  G11C16/06 ,  G11C16/3454 ,  H01L27/11582 ,  H01L29/7926

    摘要： Disclosed is a nonvolatile memory device which includes a 3D memory cell array having words lines that extend from a lowest memory cell array layer closest to a substrate to a highest memory cell array layer farthest from the substrate, a voltage generator circuit generating first and second voltage signals, and a row selecting circuit that simultaneously applies the first voltage signal to a selected word line and the second voltage signal to an unselected word line. The selected word line and the unselected word line have different resistances, yet the first voltage signal is applied to the selected word line and the second voltage signal is applied to the unselected word line with a same rising slope over a defined period of time.

    摘要翻译： 公开了一种非易失性存储器件，其包括具有从最靠近衬底的最低存储单元阵列层延伸到离衬底最远的最高存储单元阵列层的字线的3D存储单元阵列，产生第一和第二电压的电压发生器电路 信号和行选择电路，其将第一电压信号同时施加到所选字线，并将第二电压信号施加到未选字线。 所选择的字线和未选择的字线具有不同的电阻，但是第一电压信号被施加到所选择的字线，并且第二电压信号在规定的时间段内以相同的上升斜率施加到未选择的字线。

    Nonvolatile memory device and memory system including the same
    5.
    发明授权
    Nonvolatile memory device and memory system including the same 有权
    非易失性存储器件和包括其的存储器系统

    公开(公告)号：US08976591B2

    公开(公告)日：2015-03-10

    申请号：US13619118

    申请日：2012-09-14

    申请人： Sang-Wan Nam ,  Kyung-Hwa Kang ,  Junghoon Park

    发明人： Sang-Wan Nam ,  Kyung-Hwa Kang ,  Junghoon Park

    IPC分类号： G11C16/04 ,  H01L27/115

    CPC分类号： G11C16/04 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11582

    摘要： According to example embodiments, a nonvolatile memory device includes a first and a second NAND string. The first NAND string includes a first string selection transistor, a first local ground and a first global ground selection transistor, and first memory cells stacked in a direction perpendicular to a substrate. The second NAND string includes a second string selection transistor, a second local ground and a second global ground selection transistor, and second memory cells stacked in the direction perpendicular to the substrate. The device includes a selection line driver including path transistors configured to select and provide at least one operation voltage to the first and second string selection transistors, the first and second local and global ground selection transistors. The first and second string selection transistors are electrically isolated from each other, and the first and second global ground selection transistors are electrically connected.

    摘要翻译： 根据示例性实施例，非易失性存储器件包括第一和第二NAND串。 第一NAND串包括第一串选择晶体管，第一局部地和第一全局接地选择晶体管，以及沿垂直于衬底的方向堆叠的第一存储单元。 第二NAND串包括第二串选择晶体管，第二局部地和第二全局接地选择晶体管，以及沿与基板垂直的方向堆叠的第二存储单元。 该器件包括选择线驱动器，其包括被配置为选择并向第一和第二串选择晶体管，第一和第二局部和全局地选择晶体管提供至少一个操作电压的路径晶体管。 第一和第二串选择晶体管彼此电绝缘，并且第一和第二全局接地选择晶体管电连接。

    Memory devices and program methods thereof
    9.
    发明授权
    Memory devices and program methods thereof 有权
    存储器件及其编程方法

    公开(公告)号：US08625367B2

    公开(公告)日：2014-01-07

    申请号：US13476196

    申请日：2012-05-21

    申请人： Sung-Won Yun ,  ChiWeon Yoon ,  Kyung-Hwa Kang ,  JinTae Kim

    发明人： Sung-Won Yun ,  ChiWeon Yoon ,  Kyung-Hwa Kang ,  JinTae Kim

    IPC分类号： G11C5/14 ,  G11C16/00

    CPC分类号： G11C5/025 ,  G11C5/145 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/30

    摘要： Memory devices and program methods thereof, the memory devices including a memory cell array with a three-dimensional structure, a voltage generator configured to supply a pass voltage and a program voltage to the memory cell array, and a control logic configured to make the rising slope of the pass voltage variable with a program loop during a program operation. The memory device may improve a program speed by adjusting the rising slope of the pass voltage according to the program loop.

    摘要翻译： 存储器件及其编程方法，所述存储器件包括具有三维结构的存储单元阵列，被配置为向所述存储单元阵列提供通过电压和编程电压的电压发生器，以及配置为使所述上升的控制逻辑 程序运行期间程序循环的通过电压变量的斜率。 存储器件可以通过根据程序循环调整通过电压的上升沿来提高编程速度。

    Method of preparation of a catalyst for acrolein oxidation
    10.
    发明授权
    Method of preparation of a catalyst for acrolein oxidation 有权
    制备丙烯醛氧化催化剂的方法

    公开(公告)号：US06171998B2

    公开(公告)日：2001-01-09

    申请号：US09158877

    申请日：1998-09-23

    申请人： Won-Ho Lee ,  Kyung-Hwa Kang ,  Dong-Hyun Ko ,  Young-Chang Byun

    发明人： Won-Ho Lee ,  Kyung-Hwa Kang ,  Dong-Hyun Ko ,  Young-Chang Byun

    IPC分类号： B01J2300

    CPC分类号： B01J37/0036 ,  B01J23/8885 ,  B01J37/0232

    摘要： Disclosed is a method of producing a carrier catalyst for a use in acrolein oxidation reaction. Metallic salt components of the catalyst including molybdate, vanadate and tungstate are dissolved in water. An additional metallic salt component of the catalyst is added to the aqueous solution of the salts to form a suspension of the catalyst. In the suspension, the total weight of water is about 0.8 to about 5 times of the total weight of the metallic salts in the catalyst. This method of preparing suspension minimizes the amount of water required to dissolve the metallic salts, which reduces the amount of time and energy to be used in evaporating water from the suspension in the following step of obtaining catalyst. Additionally, in obtaining catalyst from the suspension prepared by this method, it is possible to avoid the deterioration of the catalytic performance since less heat is required to evaporate the water. Disclosed also is a method of producing a carrier-retained catalyst. Catalyst particles suspended in the water are split or ground into smaller particles to maintain homogeneous suspension. The suspension is sprayed to an inert carrier while applying heated air flow to remove water and obtain a carrier-retained catalyst.

    摘要翻译： 公开了一种制备用于丙烯醛氧化反应的载体催化剂的方法。 包括钼酸盐，钒酸盐和钨酸盐在内的催化剂的金属盐组分溶解在水中。 将催化剂的另外的金属盐组分加入到盐的水溶液中以形成催化剂的悬浮液。 在悬浮液中，水的总重量为催化剂中金属盐总重量的约0.8至约5倍。 这种制备悬浮液的方法使溶解金属盐所需的水量最小化，这减少了在获得催化剂的后续步骤中从悬浮液蒸发水中使用的时间和能量的量。 此外，在从通过该方法制备的悬浮液中获得催化剂的情况下，可以避免催化性能的劣化，因为需要较少的热量来蒸发水。 还公开了制备载体保留催化剂的方法。 悬浮在水中的催化剂颗粒被分裂或研磨成更小的颗粒以保持均匀的悬浮液。 将悬浮液喷雾到惰性载体上，同时施加加热的空气流以除去水并获得载体保留的催化剂。