公开(公告)号：US08298703B2

公开(公告)日：2012-10-30

申请号：US12446662

申请日：2007-10-19

申请人： Junill Yoon ,  Seung-Taek Hong ,  Seung-Jin Yang

发明人： Junill Yoon ,  Seung-Taek Hong ,  Seung-Jin Yang

IPC分类号： H01M2/02 ,  H01M2/14 ,  H01M2/16 ,  H01M2/18 ,  H01G9/00

CPC分类号： H01M2/34 ,  H01M2/0245 ,  H01M2/0262 ,  H01M2/0287 ,  H01M2/305 ,  H01M2/347

摘要： Disclosed herein is a battery module including at least one battery cell constructed in a structure in which an electrode assembly of a cathode/separator/anode structure is mounted in a battery case such that electrode leads of the electrode assembly protrude outside, wherein, when external impacts are directly or indirectly applied to the battery cell, with the result that the electrode leads move toward the electrode assembly of the battery cell, the external impacts are absorbed by the deformation of the electrode leads or the deformation of predetermined regions (‘electrode lead facing parts’) of the module in direct contact with or adjacent to the electrode leads, whereby the occurrence of a short circuit due to the contact between the electrode assembly and the electrode leads is prevented.

摘要翻译： 本文公开了一种电池模块，其包括至少一个电池单元，该电池单元构造成将阴极/隔板/阳极结构的电极组件安装在电池壳体中，使得电极组件的电极引线向外突出，其中，当外部 冲击直接或间接地施加到电池单元，结果是电极引线朝向电池单元的电极组件移动，外部冲击被电极引线的变形或预定区域的变形（电极引线面 部分）与电极引线直接接触或相邻，从而防止了由于电极组件和电极引线之间的接触引起的短路的发生。

公开(公告)号：US20100068608A1

公开(公告)日：2010-03-18

申请号：US12446662

申请日：2007-10-19

申请人： Junill Yoon ,  Seung-Taek Hong ,  Seung-Jin Yang

发明人： Junill Yoon ,  Seung-Taek Hong ,  Seung-Jin Yang

IPC分类号： H01M6/10 ,  H01M2/02

CPC分类号： H01M2/34 ,  H01M2/0245 ,  H01M2/0262 ,  H01M2/0287 ,  H01M2/305 ,  H01M2/347

摘要： Disclosed herein is a battery module including at least one battery cell constructed in a structure in which an electrode assembly of a cathode/separator/anode structure is mounted in a battery case such that electrode leads of the electrode assembly protrude outside, wherein, when external impacts are directly or indirectly applied to the battery cell, with the result that the electrode leads move toward the electrode assembly of the battery cell, the external impacts are absorbed by the deformation of the electrode leads or the deformation of predetermined regions (‘electrode lead facing parts’) of the module in direct contact with or adjacent to the electrode leads, whereby the occurrence of a short circuit due to the contact between the electrode assembly and the electrode leads is prevented.

摘要翻译： 本文公开了一种电池模块，其包括至少一个电池单元，该电池单元构造成将阴极/隔板/阳极结构的电极组件安装在电池壳体中，使得电极组件的电极引线向外突出，其中，当外部 冲击直接或间接地施加到电池单元，结果是电极引线朝向电池单元的电极组件移动，外部冲击被电极引线的变形或预定区域的变形（'电极引线 面对部件'）直接接触或邻近电极引线，由此防止了由于电极组件和电极引线之间的接触引起的短路的发生。

公开(公告)号：US08795883B2

公开(公告)日：2014-08-05

申请号：US11555743

申请日：2006-11-02

申请人： Youngjoon Shin ,  Min Su Kim ,  Junill Yoon ,  Ji Heon Ryu ,  Jeong Hee Choi ,  Seung-Jin Yang

发明人： Youngjoon Shin ,  Min Su Kim ,  Junill Yoon ,  Ji Heon Ryu ,  Jeong Hee Choi ,  Seung-Jin Yang

IPC分类号： H01M2/02 ,  H01M2/08

CPC分类号： H01M2/06 ,  H01M2/02 ,  H01M2/021 ,  H01M2/0275 ,  H01M2/0277 ,  H01M2/0287 ,  H01M2/20 ,  H01M2/266 ,  H01M2/30 ,  H01M10/052

摘要： Disclosed herein is a secondary battery constructed in a structure in which an electrode assembly having a cathode/separator/anode arrangement is mounted in a battery case made of a laminate sheet including a resin layer and a metal layer, electrode tabs of the electrode assembly are coupled to corresponding electrode leads, and the electrode assembly is sealed in the battery case while electrode leads are exposed to the outside of the battery case, wherein a protective film is attached to coupling regions between the electrode tabs and the electrode leads for sealing the coupling regions between the electrode tabs and the electrode leads. The secondary battery according to the present invention is constructed in a structure in which the coupling regions are sealed by the protective film, unlike a conventional secondary battery constructed in a structure in which the coupling regions between the electrode tabs and the electrode leads are exposed in the battery case. As a result, the electrode leads are protected from external impacts, such as falling of the battery. Consequently, no internal short circuit occurs, and therefore, the safety of the battery is increased.

摘要翻译： 本文公开了一种二次电池，其结构是将具有阴极/隔板/阳极布置的电极组件安装在由包括树脂层和金属层的层压片制成的电池壳中，电极组件的电极片 耦合到相应的电极引线，并且电极组件被密封在电池壳体中，同时电极引线暴露于电池壳体的外部，其中保护膜附接到电极接线片和电极引线之间的耦合区域，用于密封耦合 电极片和电极引线之间的区域。 根据本发明的二次电池被构造成其中耦合区域被保护膜密封的结构不同于传统的二次电池，其结构是将电极接头和电极引线之间的耦合区域暴露在其中 电池盒。 结果，电极引线被保护免受外部冲击，例如电池的掉落。 因此，不会发生内部短路，因此电池的安全性增加。

公开(公告)号：US08634249B2

公开(公告)日：2014-01-21

申请号：US13169079

申请日：2011-06-27

申请人： Seung-Jin Yang

发明人： Seung-Jin Yang

IPC分类号： G11C16/04

CPC分类号： G11C16/10 ,  G11C16/0441

摘要： A method of programming a nonvolatile memory device comprises applying positive pulses and negative pulses simultaneously to a memory cell array to program at least one memory cell included in the memory cell array.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括将正脉冲和负脉冲同时施加到存储单元阵列以对包含在存储单元阵列中的至少一个存储单元进行编程。

公开(公告)号：US20120081969A1

公开(公告)日：2012-04-05

申请号：US13169079

申请日：2011-06-27

申请人： Seung-Jin Yang

发明人： Seung-Jin Yang

IPC分类号： G11C16/10

CPC分类号： G11C16/10 ,  G11C16/0441

摘要： A method of programming a nonvolatile memory device comprises applying positive pulses and negative pulses simultaneously to a memory cell array to program at least one memory cell included in the memory cell array.

摘要翻译： 一种对非易失性存储器件进行编程的方法包括将正脉冲和负脉冲同时施加到存储单元阵列以对包含在存储单元阵列中的至少一个存储单元进行编程。

公开(公告)号：US07820516B2

公开(公告)日：2010-10-26

申请号：US11798563

申请日：2007-05-15

申请人： Seung-Jin Yang ,  Hyok-ki Kwon ,  Yong-Seok Choi ,  Jeong-Uk Han

发明人： Seung-Jin Yang ,  Hyok-ki Kwon ,  Yong-Seok Choi ,  Jeong-Uk Han

IPC分类号： H01L21/336

CPC分类号： H01L29/0692 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.

摘要翻译： 公开了一种半导体闪存单元，包括形成在半导体衬底中的第一和第二源极线，从源极线之间的衬底延伸的半导体柱，形成在半导体柱的相对侧表面上并由沟槽分隔的第一和第二电荷存储结构 隔离结构。 选择分离存储单元阵列中的相邻半导体柱的x和y间距，由此形成沟槽隔离结构用于分离电荷存储结构和设置在半导体柱的相对侧上的导电结构。 还公开了制造这种结构的方法，由此可以提高闪存器件，特别是NOR闪存器件的密度。

公开(公告)号：US20080002475A1

公开(公告)日：2008-01-03

申请号：US11798563

申请日：2007-05-15

申请人： Seung-Jin Yang ,  Hyok-ki Kwon ,  Yong-Seok Choi ,  Jeong-Uk Han

发明人： Seung-Jin Yang ,  Hyok-ki Kwon ,  Yong-Seok Choi ,  Jeong-Uk Han

IPC分类号： G11C11/34 ,  H01L21/336

CPC分类号： H01L29/0692 ,  G11C16/0416 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11568 ,  H01L29/42324 ,  H01L29/4234 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

摘要： Disclosed are pairs of semiconductor flash memory cells including first and second source lines formed in a semiconductor substrate, semiconductor pillars extending from the substrate between the source lines, first and second charge storage structures formed on opposite side surfaces of the semiconductor pillar and separated by trench isolation structures. The x and y pitch separating adjacent semiconductor pillars in the memory cell array are selected whereby forming the trench isolation structures serves to separate both charge storage structures and conductive structures provided on opposite sides of a semiconductor pillars. Also disclosed are methods of fabricating such structures whereby the density of flash memory devices, particularly NOR flash memory devices, can be improved.

摘要翻译： 公开了一种半导体闪存单元，包括形成在半导体衬底中的第一和第二源极线，从源极线之间的衬底延伸的半导体柱，形成在半导体柱的相对侧表面上并由沟槽分隔的第一和第二电荷存储结构 隔离结构。 选择分离存储单元阵列中的相邻半导体柱的x和y间距，由此形成沟槽隔离结构用于分离电荷存储结构和设置在半导体柱的相对侧上的导电结构。 还公开了制造这种结构的方法，由此可以提高闪存器件，特别是NOR闪存器件的密度。

公开(公告)号：US20070170491A1

公开(公告)日：2007-07-26

申请号：US11698658

申请日：2007-01-26

申请人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

发明人： Yong-Suk Choi ,  Jeong-Uk Han ,  Hee-Seog Jeon ,  Yong-Tae Kim ,  Seung-Jin Yang ,  Hyok-Ki Kwon

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/7881

摘要： a nonvolatile memory device Includes an active region defined in a semiconductor substrate and a control gate electrode crossing over the active region. A gate insulating layer is interposed between the control gate electrode and the active reigon. A floating gate is formed in the active region to penetrate the control gate electrode and extend to a predetermined depth into the semiconductor substrate. A tunnel insulating layer is successively interposed between the control gate electrode and the floating gate, and between the semiconductor substrate and the floating gate. The floating gate may be formed after a trench is formed by sequentially etching a control gate conductive layer and the semiconductor substrate, and a tunnel insulating layer is formed on the trench and sidewalls of the control gate conductive layer. The floating gate is formed in the trench to extend into a predetermined depth into the semiconductor substrate.

摘要翻译： 非易失性存储器件包括限定在半导体衬底中的有源区和跨越有源区的控制栅电极。 栅极绝缘层介于控制栅极电极和活性电极之间。 在有源区中形成浮栅，以穿透控制栅电极并延伸到预定深度进入半导体衬底。 隧道绝缘层被连续插入在控制栅电极和浮栅之间以及半导体衬底和浮栅之间。 可以在通过顺序蚀刻控制栅极导电层和半导体衬底形成沟槽之后形成浮置栅极，并且在控制栅极导电层的沟槽和侧壁上形成隧道绝缘层。 浮动栅极形成在沟槽中，以延伸到预定深度进入半导体衬底。

公开(公告)号：US08450809B2

公开(公告)日：2013-05-28

申请号：US12956920

申请日：2010-11-30

申请人： Seung-Jin Yang ,  Yong-Tae Kim

发明人： Seung-Jin Yang ,  Yong-Tae Kim

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L27/10 ,  H01L27/108 ,  H01L31/062

CPC分类号： H01L21/823425 ,  H01L27/112 ,  H01L27/11253 ,  H01L27/11519 ,  H01L27/11521

摘要： Provided is a semiconductor device for applying common source lines with individual bias voltages. The device includes a substrate, cell transistors arrayed in a cell matrix shape on the substrate and configured to have gate insulating patterns, gate electrodes, common source regions, drain regions and channel regions. Word lines are configured to electrically interconnect the gate electrodes with each other. Common source lines are shared between only a pair of the neighboring word lines and are configured to electrically interconnect the common source regions with each other. Drain metal contacts and source metal contacts are arranged in a straight line on the drain regions. Bit lines are electrically connected to the drain metal contacts. And impurity regions are configured to control the threshold voltage of the channel regions.

摘要翻译： 提供了一种用于以单独的偏置电压施加公共源极线的半导体器件。 该器件包括衬底，在衬底上以单元矩阵形状排列的单元晶体管，并且被配置为具有栅极绝缘图案，栅极电极，公共源极区域，漏极区域和沟道区域。 字线被配置为将栅电极彼此电互连。 公共源极线仅在一对相邻字线之间共享并且被配置为将公共源极区域彼此电互连。 漏极金属触点和源极金属触点排列在漏极区域的直线上。 位线电连接到漏极金属触点。 并且杂质区域被配置为控制沟道区域的阈值电压。

公开(公告)号：US08320184B2

公开(公告)日：2012-11-27

申请号：US12961133

申请日：2010-12-06

申请人： Seung-Jin Yang ,  Yong-Tae Kim

发明人： Seung-Jin Yang ,  Yong-Tae Kim

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： A method of programming a nonvolatile semiconductor memory device using a negative bias voltage. The method includes turning ON the string selection transistors connected to selected bit lines and turning OFF the string selection transistors connected to unselected bit lines in the same memory block, in a program mode. This can be achieved by applying a negative bias voltage to a bulk substrate and applying a voltage having a voltage level higher than the threshold voltage of string selection transistors connected to selected bit lines and lower than the threshold voltage of string selection transistors connected to unselected bit lines. The method may reduce programming disturbance between a selected cell string and an unselected cell string.

摘要翻译： 一种使用负偏置电压编程非易失性半导体存储器件的方法。 该方法包括在编程模式中接通连接到选定位线的串选择晶体管，并将连接到同一存储块中的未选择位线的串选择晶体管截止。 这可以通过将负偏置电压施加到体基板并且施加具有高于连接到选定位线的串选择晶体管的阈值电压的电压电平并且低于连接到未选位的串选择晶体管的阈值电压的电压 线条。 该方法可以减少所选择的单元串与未选择的单元串之间的编程干扰。