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    Dual layer stress liner for MOSFETS
    3.
    发明授权
    Dual layer stress liner for MOSFETS 失效
    用于MOSFET的双层应力衬垫

    公开(公告)号：US07521308B2

    公开(公告)日：2009-04-21

    申请号：US11616147

    申请日：2006-12-26

    申请人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    发明人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

    摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

    摘要翻译： 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

    DUAL LAYER STRESS LINER FOR MOSFETS
    4.
    发明申请
    DUAL LAYER STRESS LINER FOR MOSFETS 失效
    用于MOSFET的双层应力衬垫

    公开(公告)号：US20080153217A1

    公开(公告)日：2008-06-26

    申请号：US11616147

    申请日：2006-12-26

    申请人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    发明人： Deleep R. Nair ,  Christopher V. Baiocco ,  Xiangdong Chen ,  Junjung Kim ,  Jae-eun Park ,  Daewon Yang

    IPC分类号： H01L21/8234 ,  H01L21/336

    CPC分类号： H01L29/7843 ,  H01L21/31604 ,  H01L29/66575

    摘要： A method of producing a metal oxide semiconductor field effect transistor (MOSFET) creates a transistor by patterning a gate structure over a substrate, forming spacers on sides of the gate structure, and forming conductor regions within the substrate on alternate sides of the gate stack. The gate structure and the conductor regions make up the transistor. In order to reduce high power plasma induced damage, the method initially applies a first plasma having a first power level to the transistor to form a first stress layer over the transistor. After the first lower-power plasma is applied, the method then applies a second plasma having a second power level to the transistor to from a second stress layer over the first stress layer. The second power level is higher (e.g., at least 5 times higher) than the first power level.

    摘要翻译： 制造金属氧化物半导体场效应晶体管（MOSFET）的方法通过在衬底上图案化栅极结构来形成晶体管，在栅极结构的侧面上形成间隔物，以及在栅极堆叠的另一侧上在衬底内形成导体区域。 栅极结构和导体区域构成晶体管。 为了减少高功率等离子体引起的损伤，该方法首先将具有第一功率电平的第一等离子体施加到晶体管，以在晶体管上形成第一应力层。 在施加第一低功率等离子体之后，该方法然后将第二等离子体具有第二功率电平施加到第一应力层上的第二应力层至晶体管。 第二功率电平比第一功率电平高（例如，至少高5倍）。

    Electrode line structure having fine line width and method of forming the same
    5.
    发明申请
    Electrode line structure having fine line width and method of forming the same 有权
    具有细线宽度的电极线结构及其形成方法

    公开(公告)号：US20070166885A1

    公开(公告)日：2007-07-19

    申请号：US11651322

    申请日：2007-01-09

    申请人： Joo-won Lee ,  Kang-soo Chu ,  Jae-eun Park ,  Jong-ho Yang

    发明人： Joo-won Lee ,  Kang-soo Chu ,  Jae-eun Park ,  Jong-ho Yang

    IPC分类号： H01L21/00

    CPC分类号： H01L27/10888 ,  H01L23/5283 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long axis direction. The electrode lines each include a first line unit, which substantially functions as an electrode line, a second line unit, which has an inclined end in the long axis direction and is separated from the first line unit by a predetermined distance, and an insulating plug, which is interposed between the first line unit and the second line unit and electrically insulates the first line unit from the second line unit.

    摘要翻译： 在半导体器件的电极线结构及其形成方法中，电极线结构包括半导体衬底和形成在半导体衬底上并在长轴方向上具有倾斜端的电极线。 电极线各自包括基本上用作电极线的第一线单元，在长轴方向上具有倾斜端并与第一线单元隔开预定距离的第二线单元，以及绝缘插头 ，其插入在第一线路单元和第二线路单元之间，并且将第一线路单元与第二线路单元电绝缘。

    Semiconductor device having an etch stopper formed of a sin layer by low temperature ALD and method of fabricating the same
    6.
    发明授权
    Semiconductor device having an etch stopper formed of a sin layer by low temperature ALD and method of fabricating the same 有权
    具有通过低温ALD由sin层形成的蚀刻停止件的半导体器件及其制造方法

    公开(公告)号：US06858533B2

    公开(公告)日：2005-02-22

    申请号：US10612028

    申请日：2003-07-02

    申请人： Kang-soo Chu ,  J o-won Lee ,  Jae-eun Park ,  Jong-ho Yang

    发明人： Kang-soo Chu ,  J o-won Lee ,  Jae-eun Park ,  Jong-ho Yang

    IPC分类号： H01L21/28 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/318 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L21/4763

    CPC分类号： H01L21/76897 ,  H01L21/31111 ,  H01L21/31116

    摘要： Provided are a semiconductor device having an etch stopper formed of a nitride film by low temperature atomic layer deposition which can prevent damage to a semiconductor substrate and a method for fabricating the semiconductor device. Damage to the semiconductor substrate under the etch stopper composed of a second nitride film can be prevented by forming a first nitride film using high temperature LPCVD on the semiconductor substrate, forming the etch stopper including the second nitride film by low temperature ALD on the first nitride film, and removing the second nitride film by dry etching, thus taking advantage of the different etch selectivities of the first nitride film and the second nitride film.

    摘要翻译： 提供一种半导体器件，其具有通过低温原子层沉积由氮化物膜形成的蚀刻停止物，其能够防止对半导体衬底的损坏以及制造半导体器件的方法。 通过在半导体衬底上形成使用高温LPCVD的第一氮化物膜，可以防止在由第二氮化物膜构成的蚀刻停止器下的半导体衬底的损伤，通过第一氮化物上的低温ALD形成包括第二氮化物膜的蚀刻停止层 膜，并通过干蚀刻去除第二氮化物膜，从而利用第一氮化物膜和第二氮化物膜的不同蚀刻选择性。

    Electrode line structure having fine line width and method of forming the same
    9.
    发明授权
    Electrode line structure having fine line width and method of forming the same 有权
    具有细线宽度的电极线结构及其形成方法

    公开(公告)号：US07510969B2

    公开(公告)日：2009-03-31

    申请号：US11651322

    申请日：2007-01-09

    申请人： Joo-won Lee ,  Kang-soo Chu ,  Jae-eun Park ,  Jong-ho Yang

    发明人： Joo-won Lee ,  Kang-soo Chu ,  Jae-eun Park ,  Jong-ho Yang

    IPC分类号： H01L21/44

    CPC分类号： H01L27/10888 ,  H01L23/5283 ,  H01L27/10891 ,  H01L2924/0002 ,  H01L2924/00

    摘要： In an electrode line structure of a semiconductor device and a method for forming the same, the electrode line structure comprises a semiconductor substrate, and electrode lines, which are formed on the semiconductor substrate, and have an inclined end in the long axis direction. The electrode lines each include a first line unit, which substantially functions as an electrode line, a second line unit, which has an inclined end in the long axis direction and is separated from the first line unit by a predetermined distance, and an insulating plug, which is interposed between the first line unit and the second line unit and electrically insulates the first line unit from the second line unit.

    摘要翻译： 在半导体器件的电极线结构及其形成方法中，电极线结构包括半导体衬底和形成在半导体衬底上并在长轴方向上具有倾斜端的电极线。 电极线各自包括基本上用作电极线的第一线单元，在长轴方向上具有倾斜端并与第一线单元隔开预定距离的第二线单元，以及绝缘插头 ，其插入在第一线路单元和第二线路单元之间，并且将第一线路单元与第二线路单元电绝缘。