公开(公告)号：US20220302016A1

公开(公告)日：2022-09-22

申请号：US17471584

申请日：2021-09-10

Applicant: Kioxia Corporation

Inventor： Kouji MATSUO ,  Fumitaka ARAI

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11582 ,  H01L27/11573

Abstract: A semiconductor memory device includes memory block regions arranged in a first direction, a hook-up region arranged in the first direction with respect to memory block regions, and a wiring region extending in the first direction and arranged with memory block regions and the hook-up region in a second direction. Each of memory block regions includes memory strings extending in the first direction and arranged in the second direction and a first wiring extending in the second direction and connected to memory strings in common. The wiring region includes a second wiring extending in the first direction and connected to first wirings corresponding to memory block regions in common. The hook-up region includes a third wiring connected to the second wiring and a contact electrode extending in a third direction and connected to the third wiring.

公开(公告)号：US20230014439A1

公开(公告)日：2023-01-19

申请号：US17944063

申请日：2022-09-13

Applicant: Kioxia Corporation

Inventor： Keiji HOSOTANI ,  Fumitaka ARAI

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L23/522 ,  H01L23/528

Abstract: According to one embodiment, a semiconductor memory device includes the following structure. First and second semiconductor layers extend in a first direction. The second semiconductor layer is stacked apart from the first semiconductor layer in a second direction. First, second and third conductive layers and a first insulating layer extend in the second direction and intersect the first and second semiconductor layers. The first insulating layer is provided at a first distance from the first conductive layer in the first direction. The second conductive layer is provided at the first distance from the first insulating layer in the first direction. The third conductive layer is provided at the first distance from the second conductive layer in the first direction.

公开(公告)号：US20210296337A1

公开(公告)日：2021-09-23

申请号：US17016909

申请日：2020-09-10

Applicant: Kioxia Corporation

Inventor： Daisuke HAGISHIMA ,  Fumitaka ARAI ,  Keiji HOSOTANI ,  Masaki KONDO

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/11519

Abstract: According to one embodiment, a semiconductor memory device includes first and second semiconductor layers and a first conductive layer. The first and second semiconductor layers extend in a first direction. The second semiconductor layer is stacked above the first semiconductor layer in a second direction intersecting the first direction. The first conductive layer intersects the first and second semiconductor layers and extends in the second direction. The first conductive layer includes first and second portions intersecting the first and second semiconductor layers respectively. A width of the first portion in the first direction is smaller than a width of the second portion in the first direction. A thickness of the first semiconductor layer in the second direction is larger than a thickness of the second semiconductor layer in the second direction.

公开(公告)号：US20230413516A1

公开(公告)日：2023-12-21

申请号：US18458054

申请日：2023-08-29

Applicant: Kioxia Corporation

Inventor： Teruhisa SONOHARA ,  Shunichi SENO ,  Hiroki TOKUHIRA ,  Fumitaka ARAI

IPC: H10B12/00 ,  H01L29/786 ,  G11C11/4076 ,  H01L29/66 ,  G11C11/406 ,  G11C11/4096 ,  H01L21/02

CPC classification number: H10B12/30 ,  H01L29/7869 ,  G11C11/4076 ,  H01L29/66969 ,  G11C11/40615 ,  G11C11/4096 ,  H01L21/02565 ,  H10B12/03 ,  H10B12/05

Abstract: A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

公开(公告)号：US20230309311A1

公开(公告)日：2023-09-28

申请号：US17939344

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Keiji HOSOTANI ,  Fumitaka ARAI ,  Hiroaki KOSAKO ,  Takayuki KAKEGAWA ,  Shinya NAITO ,  Ryo FUKUOKA ,  Kouji MATSUO

IPC: H01L27/11573 ,  G11C16/04 ,  G11C16/08 ,  G11C16/14

CPC classification number: H01L27/11573 ,  G11C16/0466 ,  G11C16/08 ,  G11C16/14

Abstract: A semiconductor memory device includes a memory cell array and a peripheral circuit. The peripheral circuit includes a plurality of first nodes disposed corresponding to a plurality of first via electrodes, a charging circuit that charges the plurality of first nodes, a discharging circuit that discharges the plurality of first nodes, an address select circuit that electrically conducts one of the plurality of first nodes with the charging circuit or the discharging circuit in response to an input address signal, a plurality of first transistors each disposed in a current path between two of the plurality of first nodes, and a plurality of amplifier circuits that are disposed corresponding to the plurality of first via electrodes and include input terminals connected to any of the plurality of first nodes and output terminals connected to any of the plurality of first via electrodes.

公开(公告)号：US20220352188A1

公开(公告)日：2022-11-03

申请号：US17692920

申请日：2022-03-11

Applicant: Kioxia Corporation

Inventor： Ryo FUKUOKA ,  Fumitaka ARAI ,  Kouji MATSUO ,  Hiroaki KOSAKO ,  Keiji HOSOTANI ,  Takayuki KAKEGAWA ,  Shinya NAITO ,  Shinji MORI

IPC: H01L27/11519 ,  H01L27/11556 ,  G11C16/26

Abstract: A semiconductor memory device includes a first semiconductor layer, first conductive layers, electric charge accumulating portions, a first conductivity-typed second semiconductor layer, a first wiring, a second conductivity-typed third semiconductor layer, and a second conductive layer. The first semiconductor layer extends in a first direction. First conductive layers are arranged in the first direction and extend in a second direction. Electric charge accumulating portions are disposed between the first semiconductor layer and first conductive layers. The second semiconductor layer is connected to one end of the first semiconductor layer. The first wiring is connected to the first semiconductor layer via the second semiconductor layer. The third semiconductor layer is connected to a side surface in a third direction of the first semiconductor layer. The second conductive layer extends in the second direction and is connected to the first semiconductor layer via the third semiconductor layer.

公开(公告)号：US20240304548A1

公开(公告)日：2024-09-12

申请号：US18588565

申请日：2024-02-27

Applicant: Kioxia Corporation

Inventor： Toru NAKANISHI ,  Fumitaka ARAI ,  Kouji MATSUO

IPC: H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor memory device of the embodiment includes first to fourth gate electrode layers which extend in a first direction, a first semiconductor layer which extends in a second direction intersecting the first direction and is provided between the first gate electrode layer and the third gate electrode layer, and between the second gate electrode layer and the fourth gate electrode layer, a first wiring layer which extends in a third direction intersecting the first direction and the second direction and is electrically connected to the first gate electrode layer, a second wiring layer which is electrically connected to the second gate electrode layer, a third wiring layer which extends in the third direction and is electrically connected to the third gate electrode layer, and a fourth wiring layer which extends in the third direction and is electrically connected to the fourth gate electrode layer. The first wiring layer is provided between the third wiring layer and the fourth wiring layer, and the second wiring layer is provided between the first wiring layer and the fourth wiring layer.

公开(公告)号：US20220328489A1

公开(公告)日：2022-10-13

申请号：US17472902

申请日：2021-09-13

Applicant: Kioxia Corporation

Inventor： Teruhisa SONOHARA ,  Shunichi SENO ,  Hiroki TOKUHIRA ,  Fumitaka ARAI

IPC: H01L27/108 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  G11C11/406 ,  G11C11/4096 ,  G11C11/4076

Abstract: A semiconductor memory device includes: a first wiring; a first semiconductor layer connected to the first wiring, the first semiconductor layer; a first electrode, the first electrode being connected to the first semiconductor layer; a second electrode disposed between the first electrode and the first wiring, the second electrode being opposed to the first semiconductor layer; a third electrode disposed between the second electrode and the first wiring, the third electrode; a second semiconductor layer disposed between the third electrode and the first semiconductor layer, the second semiconductor layer being opposed to the third electrode; and an electric charge accumulating layer electrically connected to the first wiring via the second semiconductor layer, the electric charge accumulating layer being opposed to the first semiconductor layer.

公开(公告)号：US20220285380A1

公开(公告)日：2022-09-08

申请号：US17827107

申请日：2022-05-27

Applicant: Kioxia Corporation

Inventor： Wataru SAKAMOTO ,  Ryota SUZUKI ,  Tatsuya OKAMOTO ,  Tatsuya KATO ,  Fumitaka ARAI

IPC: H01L27/11556 ,  G11C16/04 ,  H01L27/11582 ,  H01L29/66 ,  H01L29/792 ,  H01L23/528 ,  H01L27/11519 ,  H01L29/06

Abstract: A semiconductor memory device includes two first electrode films, a first column and a second insulating film. The two first electrode films extend in a first direction and are separated from each other in a second direction. The first column is provided between the two first electrode films and has a plurality of first members and a plurality of insulating members. Each of the first members and each of the insulating members are arranged alternately in the first direction. One of the plurality of first members has a semiconductor pillar, a second electrode film and a first insulating film provided between the semiconductor pillar and the second electrode film. The semiconductor pillar, the first insulating film and the second electrode film are arranged in the second direction. The second insulating film is provided between the first column and one of the two first electrode films.

公开(公告)号：US20220246633A1

公开(公告)日：2022-08-04

申请号：US17477117

申请日：2021-09-16

Applicant: Kioxia Corporation

Inventor： Fumitaka ARAI

IPC: H01L27/11578 ,  H01L27/11551 ,  H01L27/11529 ,  H01L27/11573 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26 ,  G11C16/34 ,  G11C11/56

Abstract: According to one embodiment, a memory device includes: first and second stacks each including a first semiconductor layers arranged in a first direction perpendicular to a surface of a substrate, the first and second stacks arranged in a second direction parallel to the surface of the substrate; a second semiconductor layer above the first stack in the first direction; a third semiconductor layer above the second stack in the first direction; memory cells between the first semiconductor layers and the word lines; a first transistor on the second semiconductor layer; and a second transistor on the third semiconductor layer. The first and second stacks are arranged at a first pitch, the first and second semiconductor layers are arranged at a second pitch equal to the first pitch.