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公开(公告)号：US20240203970A1
公开(公告)日：2024-06-20
申请号：US18588611
申请日：2024-02-27
Applicant: Kioxia Corporation
Inventor： Hiroshi NAKAKI
IPC: H01L25/18 , H01L23/00 , H01L25/00 , H01L25/065 , H10B43/27
CPC classification number: H01L25/18 , H01L24/08 , H01L24/80 , H01L25/0657 , H01L25/50 , H10B43/27 , H01L2224/08145 , H01L2224/80006 , H01L2224/80894 , H01L2225/06524 , H01L2924/1431 , H01L2924/14511
Abstract: In one embodiment, a semiconductor device includes a first substrate, and a plurality of electrode layers provided above the first substrate and stacked in a first direction. The device further includes a first semiconductor layer extending in the first direction in the plurality of electrode layers, and a metal layer provided above an uppermost one of the plurality of electrode layers and extending to cross the first direction. The device further includes a second semiconductor layer including an impurity diffusion layer that is provided between the first semiconductor layer and the metal layer, electrically connects the first semiconductor layer with the metal layer, and has an impurity concentration higher than an impurity concentration of the first semiconductor layer.
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公开(公告)号：US20230397446A1
公开(公告)日：2023-12-07
申请号：US18179976
申请日：2023-03-07
Applicant: Kioxia Corporation
Inventor： Hiroshi NAKAKI , Keisuke NAKATSUKA
CPC classification number: H10B80/00 , G11C16/0483 , G11C16/08 , G11C16/26
Abstract: According to an embodiment, a semiconductor memory device includes a first memory cell array, a second memory cell array, and a row decoder. The first memory cell array includes a first select transistor, a first memory cell, a second select transistor, a first word line, a first select gate line, and a second select gate line. The second memory cell array includes, a third select transistor, a second memory cell, a fourth select transistor, a second word line, a third select gate line, a fourth select gate line. The first word line and the second word line are commonly coupled to the row decoder. The first select gate line, the second select gate line, the third select gate line, and the fourth select gate line are separately coupled to the row decoder.
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公开(公告)号：US20220285509A1
公开(公告)日：2022-09-08
申请号：US17825542
申请日：2022-05-26
Applicant: Kioxia Corporation
Inventor： Megumi ISHIDUKI , Hiroshi NAKAKI , Takamasa ITO
IPC: H01L29/423 , H01L29/66 , H01L27/11575 , H01L27/11582 , H01L27/11565 , H01L29/792
Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.
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公开(公告)号：US20220085036A1
公开(公告)日：2022-03-17
申请号：US17190348
申请日：2021-03-02
Applicant: KIOXIA CORPORATION
Inventor： Yasuhito YOSHIMIZU , Hiroshi NAKAKI , Kazuaki NAKAJIMA
IPC: H01L27/1157 , H01L23/00 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/11565 , H01L27/11578
Abstract: A semiconductor storage device includes first wiring layers stacked along a first direction, a first pillar including a first semiconductor layer and extending along the first direction through the first wiring layers, a second wiring layer disposed above the first pillar in the first direction and extending along a second direction perpendicular to the first direction, a semiconductor-containing layer including a first portion disposed on an upper end of the first pillar in the first direction, a second portion contacting the first portion and formed along the second wiring layer, and a third portion contacting an upper end of the second portion and extending along a third direction perpendicular to the first direction and crossing the second direction, and a first insulating layer between each of the first and second portions of the semiconductor-containing layer and the second wiring layer. An upper surface of the third portion contains a metal.
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公开(公告)号：US20220068961A1
公开(公告)日：2022-03-03
申请号：US17188575
申请日：2021-03-01
Applicant: KIOXIA CORPORATION
Inventor： Yasuhito YOSHIMIZU , Hiroshi NAKAKI
IPC: H01L27/11582 , H01L23/522 , H01L23/00 , H01L25/18 , H01L25/065 , H01L27/11556
Abstract: A semiconductor storage device includes first and second stacks, and first to fourth semiconductor layers. The first stack includes first conductive layers and first insulating layers alternately stacked in a first direction. The first semiconductor layer extends through the first stack. The second semiconductor layer extends in a second direction above the first stack and connected to the first semiconductor layer. The second stack includes second conductive layers and second insulating layers alternately stacked in the first direction. The first and second stacks are arranged in a third direction. The third semiconductor layer extends through the second stack. The fourth semiconductor layer extends in the second direction above the second stack and connected to the third semiconductor layer. A third conductive layer is in contact with upper surfaces of the second and fourth semiconductor layers. The second and fourth semiconductor layers are separated from each other in the third direction.
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Patent Agency Ranking
公开(公告)号：US20240306388A1
公开(公告)日：2024-09-12
申请号：US18584044
申请日：2024-02-22
Applicant: Kioxia Corporation
Inventor： Hiroshi NAKAKI
CPC classification number: H10B43/27 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/27 , H10B80/00 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A semiconductor memory device includes a stacked body, a plurality of columnar bodies, a plurality of bit lines, a plurality of contacts, and a plurality of dividing portions. The plurality of dividing portions is located separately in the third direction, each extending in the first direction in the stacked body, and dividing one or more gate electrode layers including the lowermost layer of the plurality of gate electrode layers in the third direction, when the one side is the lower side. The plurality of columnar bodies includes five columnar bodies provided in a region between two adjacent dividing portions among the plurality of dividing portions. Regarding each columnar body provided in the five columnar bodies, a separate bit line provided in the plurality of bit lines is present between a bit line provided in the plurality of bit lines and electrically connected to the columnar body, and each bit line provided in the plurality of bit lines and electrically connected to a columnar body adjacent to that columnar body at the shortest interval among the five columnar bodies.
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公开(公告)号：US20240164102A1
公开(公告)日：2024-05-16
申请号：US18393002
申请日：2023-12-21
Applicant: Kioxia Corporation
Inventor： Yasuhito YOSHIMIZU , Hiroshi NAKAKI
IPC: H10B43/27 , H01L23/00 , H01L23/522 , H01L25/065 , H01L25/18 , H10B41/27
CPC classification number: H10B43/27 , H01L23/5226 , H01L24/08 , H01L25/0657 , H01L25/18 , H10B41/27 , H01L2224/08145 , H01L2924/1431 , H01L2924/14511
Abstract: A semiconductor storage device includes first and second stacks, and first to fourth semiconductor layers. The first stack includes first conductive layers and first insulating layers alternately stacked in a first direction. The first semiconductor layer extends through the first stack. The second semiconductor layer extends in a second direction above the first stack and connected to the first semiconductor layer. The second stack includes second conductive layers and second insulating layers alternately stacked in the first direction. The first and second stacks are arranged in a third direction. The third semiconductor layer extends through the second stack. The fourth semiconductor layer extends in the second direction above the second stack and connected to the third semiconductor layer. A third conductive layer is in contact with upper surfaces of the second and fourth semiconductor layers. The second and fourth semiconductor layers are separated from each other in the third direction.
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公开(公告)号：US20240120395A1
公开(公告)日：2024-04-11
申请号：US18537954
申请日：2023-12-13
Applicant: KIOXIA CORPORATION
Inventor： Megumi ISHIDUKI , Hiroshi NAKAKI , Takamasa ITO
IPC: H01L29/423 , H01L29/66 , H01L29/792 , H10B43/10 , H10B43/27 , H10B43/50
CPC classification number: H01L29/42344 , H01L29/66833 , H01L29/7926 , H10B43/10 , H10B43/27 , H10B43/50 , H01L23/528
Abstract: A semiconductor device includes a base body, a stacked body on the base body and a first columnar part. The base body includes a substrate, a first insulating film on the substrate, a first conductive film on the first insulating film, and a first semiconductor part on the first conductive film. The stacked body includes conductive layers and insulating layers stacked alternately in a stacking direction. The first columnar part is provided inside the stacked body and the first semiconductor part. The first columnar part includes a semiconductor body and a memory film between the semiconductor body and conductive layers. The semiconductor body extends in the stacking direction. The first columnar part has a first diameter and a second diameter in a first direction crossing the stacking direction. The first diameter inside the first semiconductor part is larger than the second diameter inside the stacked body.
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公开(公告)号：US20220085050A1
公开(公告)日：2022-03-17
申请号：US17190717
申请日：2021-03-03
Applicant: Kioxia Corporation
Inventor： Hiroshi NAKAKI
IPC: H01L27/11578 , H01L27/11519 , H01L27/11524 , H01L27/11551 , H01L27/1157 , H01L27/11565 , H01L23/00
Abstract: According to one embodiment, a semiconductor storage device includes: a plurality of first wiring layers stacked in a first direction; a first memory pillar including a first semiconductor layer extending in the first direction and penetrating the plurality of first wiring layers; a second wiring layer disposed above the first semiconductor layer; a second semiconductor layer including a first part disposed between the first semiconductor layer and the second wiring layer, a second part extending away from the first semiconductor layer, and a third part provided on the second part; a first insulating layer disposed between the first part and the second wiring layer and between the second part and the second wiring layer; and a second insulating layer provided on the first insulating layer and in contact with at least a portion of the second part.
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公开(公告)号：US20240064986A1
公开(公告)日：2024-02-22
申请号：US18497435
申请日：2023-10-30
Applicant: Kioxia Corporation
Inventor： Hiroshi NAKAKI , Yasuhiro UCHIYAMA
Abstract: According to one embodiment, a memory device includes: a first conductive layer; a first conductive film extending in a first direction above the first conductive layer; a first semiconductor film extending in the first direction between the first conductive layer and the first conductive film and intersecting the first conductive layer; a second semiconductor film that is in contact with the first semiconductor film, extends in the first direction between the first conductive layer and the first conductive film, and faces the first conductive film; a first insulating film provided between the first conductive layer and the first semiconductor film; and a second insulating film provided between the first conductive film and each of the first semiconductor film and the second semiconductor film.
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