公开(公告)号：US20220246196A1

公开(公告)日：2022-08-04

申请号：US17458067

申请日：2021-08-26

Applicant: KIOXIA CORPORATION

Inventor： Hiroyuki TAKENAKA ,  Akihiko CHIBA ,  Teppei HIGASHITSUJI ,  Kiyofumi SAKURAI ,  Hiroaki NAKASA ,  Youichi MAGOME

IPC: G11C11/408 ,  G11C11/4094 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/06

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

公开(公告)号：US20250087274A1

公开(公告)日：2025-03-13

申请号：US18960230

申请日：2024-11-26

Applicant: Kioxia Corporation

Inventor： Hiroyuki TAKENAKA ,  Akihiko CHIBA ,  Teppei HIGASHITSUJI ,  Kiyofumi SAKURAI ,  Hiroaki NAKASA ,  Youichi MAGOME

IPC: G11C16/14 ,  G11C5/06 ,  G11C16/04 ,  G11C16/16 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

公开(公告)号：US20220077128A1

公开(公告)日：2022-03-10

申请号：US17184837

申请日：2021-02-25

Applicant: Kioxia Corporation

Inventor： Akihiko CHIBA ,  Takahiro TSURUDO ,  Kenichi MATOBA ,  Yoshifumi SHIMAMURA ,  Hiroaki NAKASA ,  Hiroyuki TAKENAKA

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/528

Abstract: A semiconductor storage device includes a first semiconductor chip having a first bonding surface; and a second semiconductor chip having a second bonding surface, the second bonding surface being bonded to the first bonding surface. The first semiconductor chip includes a control circuit, a first power line connected to the control circuit and extending in a first direction, and a first pad electrode disposed on the first bonding surface. The second semiconductor chip includes a second power line extending in a second direction, a third power line connected to the second power line and extending in the first direction, a second pad electrode connected to the third power line, and a third pad electrode disposed on the second bonding surface.

公开(公告)号：US20210083182A1

公开(公告)日：2021-03-18

申请号：US16803343

申请日：2020-02-27

Applicant: KIOXIA CORPORATION

Inventor： Hiroyuki HARA ,  Hiroyuki TAKENAKA ,  Akihiko CHIBA

IPC: H01L45/00 ,  G11C13/00 ,  H01L27/24

Abstract: A semiconductor memory device includes first and second wirings extending in a first direction and spaced apart from each other in the first direction, third wirings above the first and second wirings and extending in a second direction, fourth and fifth wirings above the third wirings, extending in the first direction, and spaced apart from each other in the second direction, a plurality of memory cells between each third wiring and each of first, second, fourth, and fifth wirings, voltage application circuits, connection conductors between the voltage application circuits and the wirings, and connection wirings that electrically connect the fourth and fifth wirings to the voltage application circuits. The voltage application circuits are arranged so that a non-selected voltage application circuit is under a space between the first and second wirings, and a selected voltage application circuit is under the first wiring.

公开(公告)号：US20230307395A1

公开(公告)日：2023-09-28

申请号：US17813812

申请日：2022-07-20

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA ,  Masaki UNNO ,  Hiroyuki TAKENAKA ,  Yoshiaki TAKAHASHI ,  Hiroshi MAEJIMA

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

公开(公告)号：US20240029797A1

公开(公告)日：2024-01-25

申请号：US18480305

申请日：2023-10-03

Applicant: Kioxia Corporation

Inventor： Hiroyuki TAKENAKA ,  Akihiko CHIBA ,  Teppei HIGASHITSUJI ,  Kiyofumi SAKURAI ,  Hiroaki NAKASA ,  Youichi MAGOME

IPC: G11C16/14 ,  G11C5/06 ,  G11C16/04 ,  G11C16/26 ,  G11C16/16 ,  G11C16/30 ,  G11C16/24

CPC classification number: G11C16/14 ,  G11C5/06 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/16 ,  G11C16/30 ,  G11C16/24

Abstract: A semiconductor storage device includes a first semiconductor substrate, a second semiconductor substrate, a first memory cell and a second memory cell provided between the first semiconductor substrate and the second semiconductor substrate, a first word line electrically connected to the first memory cell, a second word line electrically connected to the second memory cell, a first transistor that is provided on the first semiconductor substrate and electrically connected between the first word line and a first wiring through which a voltage is applied to the first word line, and a second transistor that is provided on the semiconductor substrate and electrically connected between the second word line and a second wiring through which a voltage is applied to the second word line.

公开(公告)号：US20210174870A1

公开(公告)日：2021-06-10

申请号：US17016185

申请日：2020-09-09

Applicant: Kioxia Corporation

Inventor： Tsuneo INABA ,  Hiroyuki TAKENAKA ,  Akihiko CHIBA

IPC: G11C13/00 ,  H01L27/24

Abstract: According to one embodiment, a semiconductor memory device includes the following configuration. First Lower word line drivers are arranged between adjacent mats, and first upper word line drivers are arranged between the first Lower word line drivers. Second Lower word line drivers are arranged between another adjacent mats, and second upper word line drivers are arranged between the second lower word line drivers. The first and second upper word line drivers are shared by the adjacent mats respectively.