公开(公告)号：US11768732B2

公开(公告)日：2023-09-26

申请号：US17530748

申请日：2021-11-19

Applicant: KIOXIA CORPORATION

Inventor： Yuta Kumano ,  Hironori Uchikawa ,  Kosuke Morinaga ,  Naoaki Kokubun ,  Masahiro Kiyooka ,  Yoshiki Notani ,  Kenji Sakurada ,  Daiki Watanabe

IPC: G11C29/00 ,  G06F11/10 ,  G11C11/56 ,  H03M13/00 ,  H03M13/37 ,  G11C29/52 ,  H03M13/11 ,  G11C29/04 ,  G11C16/26 ,  G11C29/42

CPC classification number: G06F11/1048 ,  G06F11/1012 ,  G06F11/1044 ,  G06F11/1068 ,  G11C11/5642 ,  G11C29/52 ,  H03M13/3715 ,  H03M13/3746 ,  H03M13/6325 ,  G11C16/26 ,  G11C29/42 ,  G11C2029/0409 ,  G11C2029/0411 ,  H03M13/1108 ,  H03M13/1111

Abstract: According to one embodiment, a memory system includes a non-volatile memory, a memory interface that reads data recorded in the non-volatile memory as a received value, a converting unit that converts the received value to first likelihood information by using a first conversion table, a decoder that decodes the first likelihood information, a control unit that outputs an estimated value with respect to the received value, which is a decoding result obtained by the decoding, when decoding by the decoder has succeeded, and a generating unit that generates a second conversion table based on a decoding result obtained by the decoding, when decoding of the first likelihood information by the decoder has failed. When the generating unit generates the second conversion table, the converting unit converts the received value to the second likelihood information by using the second conversion table, and the decoder decodes the second likelihood information.

公开(公告)号：US11194658B2

公开(公告)日：2021-12-07

申请号：US17117492

申请日：2020-12-10

Applicant: Kioxia Corporation

Inventor： Ryo Nogami ,  Takahiro Fujiki ,  Kosuke Morinaga ,  Naoki Wada ,  Atsushi Takayama

IPC: G06F11/00 ,  G06F11/10 ,  H03M13/37 ,  H03M13/11 ,  H03M13/15

Abstract: A semiconductor device of an embodiment includes an ECC decoding processing circuit configured to perform ECC decoding on ECC frame data in a lateral direction of a product code frame, an RS decoding processing circuit configured to perform Reed-Solomon (RS) decoding on second frame data in a longitudinal direction of the product code frame, a memory M0 in which a syndrome generated for the ECC frame data decoded is stored, a memory M1 in which an RS syndrome generated for ECC frame data for which the ECC decoding has been successful is stored, and a memory D in which ECC frame data for which the ECC decoding has been failed is stored as frame data which cannot be corrected through decoding, and frame collection processing, and iterative correction processing of performing RS decoding on the uncorrected frame data collected in the frame collection processing are executed.