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    Memory system and method
    1.
    发明授权
    Memory system and method 有权

    公开(公告)号：US12249389B2

    公开(公告)日：2025-03-11

    申请号：US17896887

    申请日：2022-08-26

    Applicant: KIOXIA CORPORATION

    Inventor： Motoki Shimizu ,  Kenji Sakurada ,  Naoto Kumano

    IPC: G11C29/52 ,  G11C8/08 ,  G11C29/02 ,  H03M13/11

    Abstract: A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.

    DYNAMIC INTERFERENCE COMPENSATION FOR SOFT DECODING IN MEMORY STORAGE DEVICES
    5.
    发明申请
    DYNAMIC INTERFERENCE COMPENSATION FOR SOFT DECODING IN MEMORY STORAGE DEVICES 有权

    公开(公告)号：US20250006265A1

    公开(公告)日：2025-01-02

    申请号：US18828352

    申请日：2024-09-09

    Applicant: Kioxia Corporation

    Inventor： Avi Steiner ,  Kenji Sakurada ,  Eyal Nitzan ,  Yasuhiko Kurosawa

    IPC: G11C16/08 ,  G11C16/04

    Abstract: Systems, methods, non-transitory computer-readable media for dynamically estimating interference compensation thresholds for read operations in non-volatile memory devices, including determining a plurality of interference states with respect to an interference source of a target row of a non-volatile memory to be read, determining compensation shifts for the plurality of interference states by determining a compensation shift for each of two or more interference states of the plurality of interference states, and applying the compensation shifts for the plurality of interference states to reading the target row.

    Memory system and method of controlling semiconductor memory device
    7.
    发明授权
    Memory system and method of controlling semiconductor memory device 有权

    公开(公告)号：US11908526B2

    公开(公告)日：2024-02-20

    申请号：US17589365

    申请日：2022-01-31

    Applicant: Kioxia Corporation

    Inventor： Naoto Kumano ,  Kenji Sakurada

    IPC: G11C16/26 ,  G11C16/04 ,  G06F11/10 ,  H10B69/00

    CPC classification number: G11C16/26 ,  G06F11/1004 ,  G11C16/0483 ,  H10B69/00

    Abstract: According to one embodiment, a memory system includes first and second memory cells and a controller. The controller obtains first and second data based on a first read operation from the first and second memory cells, respectively. The controller obtains third and fourth data based on a second read from the first and second memory cells, respectively. The second read operation is different from the first read operation in a read voltage. The controller sets first and second values indicating likelihood of data stored in the first and second memory cells, respectively, based on information indicating locations of the first and second memory cells. The controller performs error correction on data read from the first and second memory cells using at least the third data and the first value, and using at least fourth data and the second value, respectively.

    Memory system and memory controller
    8.
    发明授权
    Memory system and memory controller 有权

    公开(公告)号：US11545223B2

    公开(公告)日：2023-01-03

    申请号：US17117937

    申请日：2020-12-10

    Applicant: Kioxia Corporation

    Inventor： Kenji Sakurada ,  Naomi Takeda ,  Masanobu Shirakawa ,  Marie Takada

    IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G06F3/06 ,  G11C16/34 ,  H01L27/115

    Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

    Decoding device and decoding method
    9.
    发明授权
    Decoding device and decoding method 有权

    公开(公告)号：US11211950B2

    公开(公告)日：2021-12-28

    申请号：US17020397

    申请日：2020-09-14

    Applicant: Kioxia Corporation

    Inventor： Kuminori Hyodo ,  Kenji Sakurada ,  Yasuhiko Kurosawa ,  Takashi Nakagawa

    IPC: H03M13/45 ,  H03M13/11 ,  H03M13/00

    Abstract: According to one embodiment, a decoding device comprises a converter configured to convert read data to first likelihood information by using a first conversion table, a decoder which decodes the first likelihood information, a controller which outputs a decoding result of the decoder when the decoder succeeds decoding, and a creator module which creates a second conversion table based on the decoding result when the decoder fails decoding. When the second conversion table is created, at least a part of the decoding result is converted to second likelihood information by using the second conversion table the second likelihood information is decoded.

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