公开(公告)号：US12190967B2

公开(公告)日：2025-01-07

申请号：US17901512

申请日：2022-09-01

Applicant: Kioxia Corporation

Inventor： Takumi Fujimoto

IPC: H02M3/07 ,  G11C16/04 ,  G11C16/30 ,  G11C5/14 ,  G11C16/32

Abstract: A voltage generation circuit includes a plurality of charge pumps connected to a first node, and a control circuit that controls the number of active charge pumps among the plurality of charge pumps based on a period in which a voltage of the first node satisfies a condition.

公开(公告)号：US11763890B2

公开(公告)日：2023-09-19

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

CPC classification number: G11C16/0483 ,  G11C7/109 ,  G11C7/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US11133066B2

公开(公告)日：2021-09-28

申请号：US16934978

申请日：2020-07-21

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US11386935B2

公开(公告)日：2022-07-12

申请号：US17166910

申请日：2021-02-03

Applicant: KIOXIA CORPORATION

Inventor： Takumi Fujimoto

IPC: G11C5/14 ,  H03K19/20 ,  H02M3/07 ,  G11C8/08

Abstract: A charge pump circuit includes a first transistor having a drain connected to an input node, and a source connected to a first node; a second transistor having a drain connected to the first node, and a source connected to an output node; a first capacitor between the first and second nodes; a first inverter including an input node to which a clock signal is supplied and an output node connected to the second node via a first line; a first voltage detection circuit which includes an input node connected to the first line; a third transistor having a source connected to a third node, and a drain connected to the second node; a second inverter including an input node connected to the first voltage detection circuit and an output node connected to a fourth node via a second line; and a second capacitor between the third and fourth nodes.