公开(公告)号：US12100470B2

公开(公告)日：2024-09-24

申请号：US17897074

申请日：2022-08-26

Applicant: KIOXIA CORPORATION

Inventor： Hideyuki Kataoka

IPC: G11C7/10 ,  G11C8/08

CPC classification number: G11C7/1069 ,  G11C7/1063 ,  G11C8/08

Abstract: A semiconductor storage device includes a memory string including memory transistors and a control circuit. The control circuit is configured to in response to a first command, perform a first read operation, and in response to a second command received during the first read operation, perform a second read operation. During the first read operation, a voltage of a first selected word line is decreased from a read pass voltage to a first read voltage and then increased to the read pass voltage. During the second read operation, a voltage of a second word line is set to a second read voltage and then increased to the read pass voltage. Voltages of word lines neither selected during the first nor second read operation are maintained between the first and second read operations.

公开(公告)号：US11133066B2

公开(公告)日：2021-09-28

申请号：US16934978

申请日：2020-07-21

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US11869597B2

公开(公告)日：2024-01-09

申请号：US17464297

申请日：2021-09-01

Applicant: Kioxia Corporation

Inventor： Takeshi Nakano ,  Yuzuru Shibazaki ,  Hideyuki Kataoka ,  Junichi Sato ,  Hiroki Date

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C29/42 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24

CPC classification number: G11C16/102 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C29/42

Abstract: A semiconductor storage device in an embodiment includes a plurality of planes each including a memory cell array, a voltage generation circuit configured to apply a first intermediate voltage to an adjacent word line adjacent to a selected word line in a former half of a program period and apply a second intermediate voltage higher than the first intermediate voltage to the adjacent word line in a latter half of the program period, a discharge circuit configured to feed a discharge current from the selected word line in a period corresponding to a period in which the second intermediate voltage is applied to the adjacent word line, and a control circuit configured to set a discharge characteristic of the discharge circuit according to a number of the planes.

公开(公告)号：US11763890B2

公开(公告)日：2023-09-19

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

CPC classification number: G11C16/0483 ,  G11C7/109 ,  G11C7/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US11676673B2

公开(公告)日：2023-06-13

申请号：US17344000

申请日：2021-06-10

Applicant: Kioxia Corporation

Inventor： Hideyuki Kataoka

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10 ,  G11C16/24 ,  G11C16/30 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/3459 ,  G11C7/1048 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30

Abstract: According to one embodiment, a semiconductor memory device includes: first and second select transistors; first and second select gate lines; first and second interconnects; first and second memory cell transistors; and first and second word lines. In a write operation, after execution of a verify operation, in a period in which the second select transistor is ON, a voltage of the first word line changes from a first voltage to a second voltage and a voltage of the second word line changes from a third voltage applied in the verify operation to a fourth voltage, and after the voltage of the first word line changes to the second voltage and the voltage of the second word line changes to the fourth voltage, a voltage of the second select gate line changes from a fifth voltage to a sixth voltage.