公开(公告)号：US12193225B2

公开(公告)日：2025-01-07

申请号：US17369453

申请日：2021-07-07

Applicant: Kioxia Corporation

Inventor： Takatoshi Minamoto ,  Sho Tokairin ,  Yoshinao Suzuki

IPC: H01L27/11556 ,  G11C5/02 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device has a first conductivity type semiconductor substrate. A second conductivity type first impurity diffusion layer is disposed in a surface region of the semiconductor substrate. A resistance element is configured with a first conductivity type second impurity diffusion layer disposed in the first impurity diffusion layer in the surface region of the semiconductor substrate. In a transistor, a gate is connected to an input portion of the resistance element, a source is connected to the first impurity diffusion layer, and a drain is connected to a voltage source higher than the voltage of the input portion. A current source is connected to the source.

公开(公告)号：US11763890B2

公开(公告)日：2023-09-19

申请号：US17409584

申请日：2021-08-23

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

CPC classification number: G11C16/0483 ,  G11C7/109 ,  G11C7/24 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/28 ,  G11C16/30

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.

公开(公告)号：US11756633B2

公开(公告)日：2023-09-12

申请号：US17461848

申请日：2021-08-30

Applicant: KIOXIA CORPORATION

Inventor： Yoshinao Suzuki ,  Haruka Shibayama

IPC: G11C16/16 ,  G11C16/30 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26

Abstract: A semiconductor storage device includes a memory cell array and a voltage generation circuit configured to supply voltages of different levels to the memory cell array. The voltage generation circuit includes a first charge pump having a first characteristic and a second charge pump having a second characteristic that is substantially different from the first characteristic, and is controlled to electrically disconnect an output end of the first charge pump and an input end of the second charge pump in a first operation during which a first voltage is supplied to the memory cell array, and to electrically connect the output end of the first charge pump and the input end of the second charge pump in a second operation during which a second voltage higher than the first voltage is supplied to the memory cell array.

公开(公告)号：US11967385B2

公开(公告)日：2024-04-23

申请号：US17665391

申请日：2022-02-04

Applicant: KIOXIA CORPORATION

Inventor： Yoshinao Suzuki

IPC: G11C16/26 ,  G11C16/30

CPC classification number: G11C16/26 ,  G11C16/30

Abstract: A semiconductor storage device includes a first memory chip having a first memory cell, a first word line connected to the first memory cell, a first voltage step-up circuit, and a second voltage step-up circuit, and a second memory chip having a second memory cell, a second word line connected to the second memory cell, a third voltage step-up circuit, and a fourth voltage step-up circuit. During a read operation executed in the first memory chip, the first, second, and fourth voltage step-up circuits supply a first voltage to the first word line, and when a voltage of the first word line reaches a predetermined voltage, the first voltage step-up circuit continues to supply the first voltage to the first word line, and the second voltage step-up circuit and the fourth voltage step-up circuit stop supplying the first voltage to the first word line.

公开(公告)号：US11574672B2

公开(公告)日：2023-02-07

申请号：US17184123

申请日：2021-02-24

Applicant: Kioxia Corporation

Inventor： Yoshinao Suzuki

IPC: G11C11/4093 ,  G11C5/06 ,  G11C11/408 ,  G11C11/4074

Abstract: A semiconductor device includes a first pad, a comparison circuit, and a control circuit. A first voltage may be applicable to the first pad. The comparison circuit may include a first input terminal connected to the first pad, a second input terminal to which a second voltage is applicable, and an output terminal configured to output a comparison result between the first voltage and the second voltage. The control circuit may be configured to output, external to the semiconductor device, a signal based on the comparison result.

公开(公告)号：US11133066B2

公开(公告)日：2021-09-28

申请号：US16934978

申请日：2020-07-21

Applicant: KIOXIA CORPORATION

Inventor： Yuki Shimizu ,  Yoshihiko Kamata ,  Tsukasa Kobayashi ,  Hideyuki Kataoka ,  Koji Kato ,  Takumi Fujimoto ,  Yoshinao Suzuki ,  Yuui Shimizu

IPC: G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  G11C7/24 ,  G11C16/30 ,  G11C16/10 ,  G11C7/10 ,  G11C16/28

Abstract: A semiconductor memory device includes a substrate, first and second P-type well regions on the substrate, an N-type well region on the substrate and sandwiched between the first and second P-type well regions, a first peripheral circuit on a region of the first P-type well region adjacent to the N-type well region and supplied with a reference voltage via a first wiring, and a second peripheral circuit on a region of the second P-type well region adjacent to the N-type well region and supplied with a reference voltage via a second wiring.