公开(公告)号：US20230317709A1

公开(公告)日：2023-10-05

申请号：US18330258

申请日：2023-06-06

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA ,  Tetsuaki UTSUMI

IPC: H01L25/18 ,  H01L23/00 ,  G11C16/30

CPC classification number: H01L25/18 ,  H01L24/09 ,  H01L24/05 ,  H01L24/03 ,  G11C16/30 ,  H01L24/08 ,  G11C16/0483

Abstract: A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.

公开(公告)号：US20210118862A1

公开(公告)日：2021-04-22

申请号：US17012111

申请日：2020-09-04

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L25/065 ,  H01L23/00

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

公开(公告)号：US20240113058A1

公开(公告)日：2024-04-04

申请号：US18538659

申请日：2023-12-13

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA ,  Toshiki HISADA

IPC: H01L23/00 ,  G11C16/04 ,  G11C16/08 ,  G11C16/24 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L24/08 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/24 ,  H01L25/0657 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor storage device includes first and second chips. The first chip includes a first semiconductor substrate, first conductive layers arranged in a first direction and extending in a second direction, a semiconductor column extending in the first direction and facing the first conductive layers, a first charge storage film formed between the first conductive layers and the semiconductor column, a plurality of first transistors on the first semiconductor substrate, and first bonding electrodes electrically connected to a portion of the plurality of first transistors. The second chip includes a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, and second bonding electrodes electrically connected to a portion of the plurality of second transistors, and bonded to the first bonding electrodes. A thickness of the second semiconductor substrate in the first direction is smaller than a thickness of the first semiconductor substrate in the first direction.

公开(公告)号：US20220077088A1

公开(公告)日：2022-03-10

申请号：US17183809

申请日：2021-02-24

Applicant: KIOXIA CORPORATION

Inventor： Nobuaki OKADA ,  Toshiki HISADA

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L27/11556 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/08

Abstract: A semiconductor storage device includes first and second chips. The first chip includes a first semiconductor substrate, first conductive layers arranged in a first direction and extending in a second direction, a semiconductor column extending in the first direction and facing the first conductive layers, a first charge storage film formed between the first conductive layers and the semiconductor column, a plurality of first transistors on the first semiconductor substrate, and first bonding electrodes electrically connected to a portion of the plurality of first transistors. The second chip includes a second semiconductor substrate, a plurality of second transistors on the second semiconductor substrate, and second bonding electrodes electrically connected to a portion of the plurality of second transistors, and bonded to the first bonding electrodes. A thickness of the second semiconductor substrate in the first direction is smaller than a thickness of the first semiconductor substrate in the first direction.

公开(公告)号：US20210082897A1

公开(公告)日：2021-03-18

申请号：US17003694

申请日：2020-08-26

Applicant: KIOXIA CORPORATION

Inventor： Nobuaki OKADA ,  Tetsuaki UTSUMI

IPC: H01L25/18 ,  H01L23/00 ,  G11C16/30

Abstract: A semiconductor storage device includes first and second chips and first and second power supply electrodes. The first chip includes conductive layers arranged in a first direction, a semiconductor pillar extending in the first direction and facing the conductive layers, first contacts extending in the first direction and connected to the conductive layers, second contacts extending in the first direction and connected to a first power supply electrode, third contacts extending in the first direction, facing the second contacts in a direction crossing the first direction, and connected to the second power supply electrode, and first bonding electrodes connected to the first contacts. The second chip includes a semiconductor substrate, transistors provided on the semiconductor substrate, fourth contacts connected to the transistors, and second bonding electrodes connected to the fourth contacts. The first and second chips are bonded together so that respective first and second bonding electrodes are connected together.

公开(公告)号：US20230307434A1

公开(公告)日：2023-09-28

申请号：US18203952

申请日：2023-05-31

Applicant: Kioxia Corporation

Inventor： Hiroshi MAEJIMA ,  Katsuaki ISOBE ,  Nobuaki OKADA ,  Hiroshi NAKAMURA ,  Takahiro TSURUDO

IPC: H01L25/18 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L25/18 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  H01L24/08 ,  H01L25/0657 ,  H01L2924/14511 ,  H01L2224/08145 ,  H01L2924/1431

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

公开(公告)号：US20230307395A1

公开(公告)日：2023-09-28

申请号：US17813812

申请日：2022-07-20

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA ,  Masaki UNNO ,  Hiroyuki TAKENAKA ,  Yoshiaki TAKAHASHI ,  Hiroshi MAEJIMA

IPC: H01L23/00 ,  H01L25/18 ,  H01L25/065

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

公开(公告)号：US20240250026A1

公开(公告)日：2024-07-25

申请号：US18596742

申请日：2024-03-06

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA

IPC: H01L23/528 ,  G11C16/04 ,  G11C16/30 ,  H01L23/522 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00

CPC classification number: H01L23/5283 ,  G11C16/0483 ,  G11C16/30 ,  H01L23/5223 ,  H01L23/5226 ,  H01L25/0657 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06506

Abstract: A semiconductor memory device includes: a substrate; a first wiring layer including a first conductive layer and a second conductive layer; a second wiring layer disposed between the substrate and the first wiring layer; and a memory cell array layer disposed between the substrate and the second wiring layer. The memory cell array layer includes: a plurality of third conductive layers arranged in a first direction intersecting with a surface of the substrate; a semiconductor layer extending in the first direction and opposed to the plurality of third conductive layers; and an electric charge accumulating layer disposed between the plurality of third conductive layers and the semiconductor layer. The second wiring layer includes: a fourth conductive layer connected to one end portion of the semiconductor layer in the first direction; and a fifth conductive layer opposed to the first conductive layer and electrically connected to the second conductive layer.

公开(公告)号：US20240074214A1

公开(公告)日：2024-02-29

申请号：US18455937

申请日：2023-08-25

Applicant: KIOXIA CORPORATION

Inventor： Nobuaki OKADA ,  Akihiko CHIBA ,  Kenichi MATOBA ,  Haruna SUGIURA

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A semiconductor memory device includes a plurality of transistors arranged in a first direction, and arranged in a second direction and a first wiring layer disposed between a semiconductor substrate and a plurality of voltage supply wirings. Each of the plurality of transistors includes a source region and a drain region. The first wiring layer includes a plurality of first connecting portions disposed at positions overlapping with the plurality of source regions when viewed in a third direction and electrically connected to the plurality of source regions and the plurality of voltage supply wirings, a plurality of second connecting portions disposed at positions overlapping with the plurality of source regions when viewed in the third direction and electrically connected to a plurality of the drain regions and a plurality of conductive layers, and a passing wiring region disposed between a pair of the second connecting portions.

公开(公告)号：US20230307397A1

公开(公告)日：2023-09-28

申请号：US17930149

申请日：2022-09-07

Applicant: Kioxia Corporation

Inventor： Nobuaki OKADA

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/08 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/08146 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/14511

Abstract: According to one embodiment, a device includes a first chip including a first via in a first surface; and a second chip including a second via in a second surface and overlapping the first chip in a direction perpendicular to the first surface. The first via includes a first side along a second direction parallel to the first surface, and a second side along a third direction parallel to the first surface, the second via includes a third side along the third direction and a fourth side along the second direction, a dimension of the first side is larger than a dimension of the second side, a dimension of the third side is larger than a dimension of the fourth side. The first via is in contact with the second via so that the first side intersects the third side.