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    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    3.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US07250669B2

    公开(公告)日：2007-07-31

    申请号：US10909523

    申请日：2004-08-02

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L29/00

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    4.
    发明授权
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 失效
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US06869884B2

    公开(公告)日：2005-03-22

    申请号：US10225828

    申请日：2002-08-22

    申请人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Hwei Ng ,  Purakh Verma ,  Jia Zhen Zheng ,  Johnny Chew ,  Choon Beng Sia

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+ or O2+ are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。

    Method of fabricating circular or angular spiral MIM capacitors
    8.
    发明申请
    Method of fabricating circular or angular spiral MIM capacitors 审中-公开
    制造圆形或角螺旋MIM电容器的方法

    公开(公告)号：US20050086780A1

    公开(公告)日：2005-04-28

    申请号：US10692029

    申请日：2003-10-23

    申请人： Kai Shao ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Sanford Chu

    发明人： Kai Shao ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Sanford Chu

    IPC分类号： H01L27/08 ,  H01G7/00 ,  H01K3/10

    CPC分类号： H01L27/0805 ,  Y10T29/43 ,  Y10T29/435 ,  Y10T29/49165

    摘要： A method of forming a capacitor comprising the following steps. A substrate having a lower low-k dielectric layer formed thereover is provided with the lower low-k dielectric layer having a dielectric constant of less than about 3.0. Metal vertical electrode plates are formed within the lower low-k dielectric layer so that the adjacent metal vertical electrode plates have lower low-k dielectric layer portions therebetween. The lower low-k dielectric layer portions between the adjacent metal vertical electrode plates are replaced with high-k dielectric material trench portions having a dielectric constant of greater than about 3.0.

    摘要翻译： 一种形成电容器的方法，包括以下步骤。 具有形成在其上的下部低k电介质层的衬底设置有介电常数小于约3.0的下部低k电介质层。 金属垂直电极板形成在下部低k电介质层内，使得相邻的金属垂直电极板之间具有较低的低k电介质层部分。 在相邻的金属垂直电极板之间的较低的低k电介质层部分被具有大于约3.0的介电常数的高k电介质材料沟槽部分代替。

    METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER
    9.
    发明申请
    METHOD OF MAKING DIRECT CONTACT ON GATE BY USING DIELECTRIC STOP LAYER 失效
    通过使用介质停止层在门上制造直接接触的方法

    公开(公告)号：US20050059216A1

    公开(公告)日：2005-03-17

    申请号：US10664211

    申请日：2003-09-17

    申请人： Purakh Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    发明人： Purakh Verma ,  Sanford Chu ,  Lap Chan ,  Yelehanka Ramachandramurthy Pradeep ,  Kai Shao ,  Jia Zheng

    IPC分类号： H01L21/00 ,  H01L21/3205 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/768 ,  H01L21/84 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L21/76802 ,  H01L21/76829

    摘要： A CMOS RF device and a method to fabricate said device with low gate contact resistance are described. Conventional MOS transistor is first formed with isolation regions, poly-silicon gate structure, sidewall spacers around poly gate, and implanted source/drain with lightly and heavily doped regions. A silicon dioxide layer such as TEOS is deposited, planarized with chemical mechanical polishing (CMP) to expose the gate and treated with dilute HF etchant to recess the silicon dioxide layer below the surface of the gate. Silicon nitride is then deposited and planarized with CMP and then etched except around the gates, using a oversize poly-silicon gate mask. Inter-level dielectric mask is then deposited, contact holes etched, and contact metal is deposited to form the transistor. During contact hole etch over poly-silicon gate, silicon nitride around the poly gate acts as an etch stop. Resulting structure with direct gate contact achieves significantly reduced gate resistance and thereby improved noise performance at high frequency operation, increased unit power gain frequency (f.,), and reduced gate delay.

    摘要翻译： 描述CMOS RF器件和制造具有低栅极接触电阻的所述器件的方法。 传统的MOS晶体管首先形成有隔离区域，多晶硅栅极结构，围绕多晶硅栅极的侧壁隔离物以及具有轻掺杂和重掺杂区域的注入源极/漏极。 沉积诸如TEOS的二氧化硅层，通过化学机械抛光（CMP）平坦化以暴露栅极，并用稀的HF蚀刻剂处理以使位于栅极表面下方的二氧化硅层凹陷。 然后将氮化硅沉积并用CMP平坦化，然后使用超大型多晶硅栅极掩模在栅极周围进行蚀刻。 然后沉积层间电介质掩模，蚀刻接触孔，并沉积接触金属以形成晶体管。 在多晶硅栅极的接触孔蚀刻期间，多晶硅周围的氮化硅作为蚀刻停止。 具有直接栅极接触的所得结构实现了显着降低的栅极电阻，从而改善了高频操作时的噪声性能，增加的单位功率增益频率（f。）和减小的栅极延迟。

    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks
    10.
    发明申请
    Process to reduce substrate effects by forming channels under inductor devices and around analog blocks 有权
    通过在电感器件和模拟块周围形成沟道来减少衬底效应的过程

    公开(公告)号：US20050009357A1

    公开(公告)日：2005-01-13

    申请号：US10909523

    申请日：2004-08-02

    申请人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

    发明人： Lap Chan ,  Sanford Chu ,  Chit Ng ,  Purakh Verma ,  Jia Zheng ,  Johnny Chew ,  Choon Sia

    IPC分类号： H01L21/20 ,  H01L21/265 ,  H01L21/302 ,  H01L21/461 ,  H01L21/764

    CPC分类号： H01L21/764 ,  H01L21/26506

    摘要： A first method of reducing semiconductor device substrate effects comprising the following steps. O+or O2+are selectively implanted into a silicon substrate to form a silicon-damaged silicon oxide region. One or more devices are formed over the silicon substrate proximate the silicon-damaged silicon oxide region within at least one upper dielectric layer. A passivation layer is formed over the at least one upper dielectric layer. The passivation layer and the at least one upper dielectric layer are patterned to form a trench exposing a portion of the silicon substrate over the silicon-damaged silicon oxide region. The silicon-damaged silicon oxide region is selectively etched to form a channel continuous and contiguous with the trench whereby the channel reduces the substrate effects of the one or more semiconductor devices. A second method of reducing substrate effects under analog devices includes forming an analog device on a SOI substrate and then selectively etching the silicon oxide layer of the SOI substrate to form a channel at least partially underlying the analog device.

    摘要翻译： 降低半导体器件衬底效应的第一种方法包括以下步骤。 O +或O 2 +被选择性地注入到硅衬底中以形成硅损坏的氧化硅区域。 在硅衬底附近，在至少一个上部电介质层内的硅损坏的氧化硅区域附近形成一个或多个器件。 在所述至少一个上介电层上形成钝化层。 图案化钝化层和至少一个上电介质层以形成在硅损坏的氧化硅区域上暴露硅衬底的一部分的沟槽。 选择性地蚀刻硅损坏的氧化硅区域以形成与沟槽连续且邻接的沟道，由此沟道减小了一个或多个半导体器件的衬底效应。 减少模拟器件下的衬底效应的第二种方法包括在SOI衬底上形成模拟器件，然后选择性地蚀刻SOI衬底的氧化硅层，以形成至少部分在模拟器件下面的沟道。