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    Method for simultaneously forming a through silicon via and a deep trench structure
    1.
    发明授权
    Method for simultaneously forming a through silicon via and a deep trench structure 有权
    同时形成硅通孔和深沟槽结构的方法

    公开(公告)号：US08492241B2

    公开(公告)日：2013-07-23

    申请号：US12904348

    申请日：2010-10-14

    申请人： Kangguo Cheng ,  Mukta G Farooq ,  Louis L Hsu

    发明人： Kangguo Cheng ,  Mukta G Farooq ,  Louis L Hsu

    IPC分类号： H01L21/8249 ,  H01L21/76

    CPC分类号： H01L27/0207 ,  G06F17/5081 ,  H01L21/743 ,  H01L21/76898

    摘要： A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.

    摘要翻译： 通过单个掩模和单个反应离子蚀刻（RIE）同时在同一衬底上形成贯通硅通孔（TSV）和深沟槽电容器（DTCap）或深沟槽隔离（DTI）。 TSV沟槽比DTCap或DTI沟槽更宽更深。 TSV和DTCap或DTI在沟槽侧壁上形成有不同的介电材料。 TSV和DTCap或DTI完全对齐。

    Programmable anti-fuse structures with conductive material islands
    10.
    发明授权
    Programmable anti-fuse structures with conductive material islands 失效
    具有导电材料岛的可编程抗熔丝结构

    公开(公告)号：US08471356B2

    公开(公告)日：2013-06-25

    申请号：US12761780

    申请日：2010-04-16

    申请人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

    发明人： Kangguo Cheng ,  Louis L. Hsu ,  William R. Tonti ,  Chih-Chao Yang

    IPC分类号： G06F17/50 ,  H01L21/768 ,  H01L23/525

    CPC分类号： H01L23/5252 ,  G06F17/505 ,  H01L2924/0002 ,  H01L2924/00

    摘要： Voltage programmable anti-fuse structures and methods are provided that include at least one conductive material island atop a dielectric surface that is located between two adjacent conductive features. In one embodiment, the anti-fuse structure includes a dielectric material having at least two adjacent conductive features embedded therein. At least one conductive material island is located on an upper surface of the dielectric material that is located between the at least two adjacent conductive features. A dielectric capping layer is located on exposed surfaces of the dielectric material, the at least one conductive material island and the at least two adjacent conductive features. When the anti-fuse structure is in a programmed state, a dielectric breakdown path is present in the dielectric material that is located beneath the at least one conductive material island which conducts electrical current to electrically couple the two adjacent conductive features.

    摘要翻译： 提供了电压可编程的抗熔丝结构和方法，其包括位于介于两个相邻导电特征之间的电介质表面上的至少一个导电材料岛。 在一个实施例中，反熔丝结构包括具有嵌入其中的至少两个相邻导电特征的电介质材料。 至少一个导电材料岛位于介电材料的位于至少两个相邻导电特征之间的上表面上。 电介质覆盖层位于电介质材料的暴露表面上，至少一个导电材料岛和至少两个相邻的导电特征。 当反熔丝结构处于编程状态时，介电击穿路径存在于介电材料中，介电材料位于至少一个导电材料岛之下，该导电材料岛传导电流以电耦合两个相邻导电特征。