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    Method for simultaneously forming a through silicon via and a deep trench structure
    7.
    发明授权
    Method for simultaneously forming a through silicon via and a deep trench structure 有权
    同时形成硅通孔和深沟槽结构的方法

    公开(公告)号：US08492241B2

    公开(公告)日：2013-07-23

    申请号：US12904348

    申请日：2010-10-14

    申请人： Kangguo Cheng ,  Mukta G Farooq ,  Louis L Hsu

    发明人： Kangguo Cheng ,  Mukta G Farooq ,  Louis L Hsu

    IPC分类号： H01L21/8249 ,  H01L21/76

    CPC分类号： H01L27/0207 ,  G06F17/5081 ,  H01L21/743 ,  H01L21/76898

    摘要： A through silicon via (TSV) and a deep trench capacitor (DTCap) or a deep trench isolation (DTI) are simultaneously formed on the same substrate by a single mask and a single reactive ion etching (RIE). The TSV trench is wider and deeper that the DTCap or DTI trench. The TSV and DTCap or DTI are formed with different dielectric materials on the trench sidewalls. The TSV and DTCap or DTI are perfectly aligned.

    摘要翻译： 通过单个掩模和单个反应离子蚀刻（RIE）同时在同一衬底上形成贯通硅通孔（TSV）和深沟槽电容器（DTCap）或深沟槽隔离（DTI）。 TSV沟槽比DTCap或DTI沟槽更宽更深。 TSV和DTCap或DTI在沟槽侧壁上形成有不同的介电材料。 TSV和DTCap或DTI完全对齐。

    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures
    9.
    发明授权
    Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures 失效
    具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法

    公开(公告)号：US07898014B2

    公开(公告)日：2011-03-01

    申请号：US11393142

    申请日：2006-03-30

    申请人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    发明人： Kangguo Cheng ,  Louis Lu-Chen Hsu ,  Jack Allan Mandelman

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10841 ,  H01L27/10864

    摘要： Semiconductor device structures with self-aligned doped regions and methods for forming such semiconductor device structures. The semiconductor structure comprises first and second doped regions of a first conductivity type defined in the semiconductor material of a substrate bordering a sidewall of a trench. An intervening region of the semiconductor material separates the first and second doped regions. A third doped region is defined in the semiconductor material bordering the sidewall of the trench and disposed between the first and second doped regions. The third doped region is doped to have a second conductivity type opposite to the first conductivity type. Methods for forming the doped regions involve depositing either a layer of a material doped with both dopants or different layers each doped with one of the dopants in the trench and, then, diffusing the dopants from the layer or layers into the semiconductor material bordering the trench sidewall.

    摘要翻译： 具有自对准掺杂区域的半导体器件结构和用于形成这种半导体器件结构的方法。 半导体结构包括限定在与沟槽的侧壁相邻的衬底的半导体材料中的第一导电类型的第一和第二掺杂区域。 半导体材料的中间区域分离第一和第二掺杂区域。 第三掺杂区域限定在与沟槽的侧壁接壤并且设置在第一和第二掺杂区域之间的半导体材料中。 第三掺杂区被掺杂以具有与第一导电类型相反的第二导电类型。 用于形成掺杂区域的方法包括沉积掺杂有掺杂剂或不同层的材料的层，每个掺杂剂或不同的层在沟槽中掺杂有一种掺杂剂，然后将掺杂剂从层或层扩散到与沟槽接壤的半导体材料 侧壁。