公开(公告)号：US5492266A

公开(公告)日：1996-02-20

申请号：US298983

申请日：1994-08-31

申请人： Karl G. Hoebener ,  Eric M. Hubacher ,  Julian P. Partridge

发明人： Karl G. Hoebener ,  Eric M. Hubacher ,  Julian P. Partridge

IPC分类号： B41F15/08 ,  B23K3/06 ,  B41M1/12 ,  H01L21/48 ,  H01L21/60 ,  H01L23/485 ,  H05K3/12 ,  H05K3/34 ,  B23K1/00

CPC分类号： H05K3/3484 ,  B23K3/06 ,  H01L21/4853 ,  H01L24/11 ,  H01L24/13 ,  H01L24/81 ,  H05K3/1225 ,  B23K2201/36 ,  H01L2224/11 ,  H01L2224/1131 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787 ,  H05K2201/09727 ,  H05K2201/10674 ,  H05K2203/043 ,  H05K2203/0485 ,  H05K2203/0557 ,  H05K2203/1476 ,  H05K3/1216

摘要： A method, and product created thereby, by which low melting point solder suitable for reflow connection of components is formed on select contacts of a printed circuit board. The method is particularly suited to the fabrication of populated printed circuit board having fine pitch devices including flip-chip devices, connected on a board including conventional coarse pitch surface mounted components. The fine pitch contacts of the board are exposed through holes in a stencil characterized in its ability to withstand solder reflow temperatures, not be wettable by solder, and have a coefficient of thermal expansion relatively matching the printed circuit board. Low temperature solder paste is screen deposited into the stencil openings. With the stencil fixedly positioned on the board, the solder paste retained by the stencil pattern is reflowed to selectively form on the underlying contacts of the printed circuit board. Thereafter, according to a preferred practice of the invention, the stencil is removed from the board and the board is subject to previously practiced depositions of flux and paste in preparation for fine and coarse pitch component placement and ensuing solder reflow. Alternate practices of the invention involve concurrent deposition of fine and coarse pitch solder and retention of the stencil following fine pitch solder fellow.

摘要翻译： 一种由此制造的产品，通过这种方法，在印刷电路板的选择的触点上形成适用于部件回流连接的低熔点焊料。 该方法特别适用于制造具有细间距器件的填充印刷电路板，其中包括倒装芯片器件，其连接在包括常规粗节距表面安装部件的板上。 板的细间距触点通过模板中的孔露出，其特征在于其能够承受焊料回流温度，不能被焊料润湿，并且具有与印刷电路板相对匹配的热膨胀系数。 低温焊膏被屏幕沉积在模板孔中。 当模板固定在板上时，由模板图案保持的焊膏被回流以选择性地形成在印刷电路板的下面的触点上。 此后，根据本发明的优选实践，将模板从板上移除，并且板经历先前实践的焊剂和浆料沉积，以准备精细和粗略的沥青组分放置以及随后的回流焊。 本发明的替代实践涉及精细和粗沥青焊料的同时沉积以及在细间距焊料之后保留模板。

公开(公告)号：US5762259A

公开(公告)日：1998-06-09

申请号：US848792

申请日：1997-05-01

申请人： Eric M. Hubacher ,  Karl G. Hoebener

发明人： Eric M. Hubacher ,  Karl G. Hoebener

IPC分类号： H01L21/60 ,  H05K3/12 ,  H05K3/34 ,  B23K35/00 ,  H01L21/441

CPC分类号： H01L24/11 ,  H05K3/3484 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/3025 ,  H05K2203/0113 ,  H05K2203/0338 ,  H05K2203/043 ,  H05K2203/0557 ,  H05K3/1216

摘要： Solder bumps are formed on a substrate, such as a semiconductor die (28) or wafer, using a screen printing and reflow operation. Solder paste (18) is screened into openings (14) of a stencil (10). The paste is reflowed within the stencil to produce a solder preform (22). The stencil and solder preforms are then aligned over the substrate to be bumped so that the preform aligns with a metal pad (30) on the substrate. The solder preforms are again reflowed, and the solder within the openings of the stencil is drawn onto the metal pad. To facilitate the transfer of the solder from the stencil to the metal pad, a second stencil (12) can be used to form a protrusion (27) on the solder preform. The protrusion contacts the metal pad during the transfer reflow operation to facilitate removing the solder from the stencil.

摘要翻译： 使用丝网印刷和回流操作在诸如半导体管芯（28）或晶片的基板上形成焊料凸块。 焊膏（18）被筛选到模版（10）的开口（14）中。 在模板内将浆料回流以产生焊料预制件（22）。 然后将模板和焊料预成型件对准在衬底上以被凸起，使得预成型体与衬底上的金属焊盘（30）对准。 焊料预制件再次回流，并且模板的开口内的焊料被拉到金属垫上。 为了便于将焊料从模板转移到金属焊盘，可以使用第二模板（12）在焊料预成型件上形成突起（27）。 在转移回流操作期间，突起与金属垫接触以便于从模板去除焊料。

公开(公告)号：US5554940A

公开(公告)日：1996-09-10

申请号：US270880

申请日：1994-07-05

申请人： Eric M. Hubacher

发明人： Eric M. Hubacher

IPC分类号： G01R1/067 ,  G01R1/073 ,  H01L21/60 ,  H01L21/66 ,  G01R31/26

CPC分类号： G01R1/07392 ,  G01R1/07314 ,  H01L24/06 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01076 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/05042 ,  H01L2924/14

摘要： Probing array bumped semiconductor devices using cantilever probe needles is facilitated by the formation of peripheral test pads. A semiconductor die (10) includes bond pads (12). A redistribution metallization layer is deposited and patterned to form individual redistribution structures (26) associated with and electrically coupled to each bond pad. Each redistribution structure includes a test pad (28), a bump pad (30) and a bump pad interconnect (32). The test pads are formed in positions close to those of the underlying bond pads, while the bump pads can be formed anywhere within the die. Having the test pads located similarly to the bond pads enables the same or a similar probe card apparatus and cantilever needles (50) to probe the die either at the bond pads for devices which are to be wire bonded or TAB bonded, or at the test pads for devices which are to be bumped.

摘要翻译： 通过外围测试焊盘的形成，便于利用悬臂探针探测阵列凸起的半导体器件。 半导体管芯（10）包括接合焊盘（12）。 重新分布金属化层被沉积并图案化以形成与每个接合焊盘相关联并电耦合到每个接合焊盘的单独再分配结构（26）。 每个再分布结构包括测试焊盘（28），凸块焊盘（30）和凸块焊盘互连（32）。 测试焊盘形成在接近底层接合焊盘的位置，而焊盘可以在模具内的任何位置形成。 使测试垫与接合垫类似，使得相同或相似的探针卡装置和悬臂针（50）可以在用于要接线或TAB键合的装置的接合垫处或在测试中探测模具 将被撞击的装置的垫片。

公开(公告)号：US4038599A

公开(公告)日：1977-07-26

申请号：US537514

申请日：1974-12-30

申请人： Ronald Bove ,  Eric M. Hubacher

发明人： Ronald Bove ,  Eric M. Hubacher

IPC分类号： G01R31/26 ,  G01R1/073 ,  G01R31/28 ,  H01L21/66 ,  G01R31/02

CPC分类号： G01R31/2853 ,  G01R1/07314 ,  G01R31/2886

摘要： A contactor structure employed in a high speed electronic test system for testing the electrical integrity of the conductive paths (or lines) in the packaging substrate prior to the mounting and connection thereto of the high circuit density monolithic devices. The contactor structure includes a semiconductor space transformer fabricated by large scale integration techniques and containing a plurality of discrete first integrated circuits. The first integrated circuits of the space transformer being respectively electrically connected to said electrical probes. Second integrated circuitry interconnecting said first integrated circuits is also contained within said semiconductor space transformer. Under control of said test system said second integrated circuitry selectively energizes, selected first and second ones of said first integrated circuits. Each of said first integrated circuits contains circuitry, whereby said selected first and second ones of said first circuits will manifest the electrical integrity of the electrical path there between.

公开(公告)号：US5536677A

公开(公告)日：1996-07-16

申请号：US348009

申请日：1994-12-01

申请人： Eric M. Hubacher

发明人： Eric M. Hubacher

IPC分类号： H01L21/60 ,  H01L23/485 ,  H01L21/285 ,  H01L21/321

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L2224/13099 ,  H01L2224/13109 ,  H01L2224/13116 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/1433 ,  Y10S438/944

摘要： A method for forming conductive bumps (60, 62) on a semiconductor device (50) using a mask structure (20) employs two masks (22, 24) individually fabricated and positioned in a back-to-back relationship. Each mask is patterned and isotropically etched to form a plurality of tapered openings (30, 40) corresponding to a pattern of terminal pads (54) on the semiconductor device. Metal is evaporated through the openings and onto the terminal pads. The mask structure is removed and the remaining metal is reflowed to form the conductive bumps. Using a mask structure having two individual masks (each with a thickness of one-half a typical mask thickness) enables smaller openings to be etched in each mask. Upon joining the two masks, the effective aspect ratio of the mask structure is reduced to produce smaller and denser conductive bumps without loss of volume and height control.

摘要翻译： 使用掩模结构（20）在半导体器件（50）上形成导电凸块（60,62）的方法使用分别制造并以背靠背关系定位的两个掩模（22,24）。 对每个掩模进行图案化和各向同性蚀刻以形成对应于半导体器件上的端子焊盘（54）的图案的多个锥形开口（30,40）。 通过开口将金属蒸发到端子焊盘上。 去除掩模结构并且剩余的金属回流以形成导电凸块。 使用具有两个单独掩模（每个具有典型掩模厚度的二分之二的厚度）的掩模结构能够在每个掩模中蚀刻更小的开口。 在连接两个掩模时，掩模结构的有效长宽比被减小以产生更小且更致密的导电凸块，而不会损失体积和高度控制。