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    Memory device with a selection element and a control line in a substantially similar layer
    3.
    发明授权
    Memory device with a selection element and a control line in a substantially similar layer 有权
    具有选择元件和控制线的存储器件在基本相似的层中

    公开(公告)号：US07391064B1

    公开(公告)日：2008-06-24

    申请号：US11001519

    申请日：2004-12-01

    申请人： Nicholas H. Tripsas ,  Suzette Pangrle

    发明人： Nicholas H. Tripsas ,  Suzette Pangrle

    IPC分类号： H01L29/80

    CPC分类号： H01L27/1021 ,  H01L27/101

    摘要： The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wordline and bitline). In one embodiment of the invention, a diode is implemented as the selection element within the same layer as one of the control lines. Production of the selection element within the same layer as one of the wordline and bitline reduces problems associated with vertical stacking, increases device yield and reduces related production costs. The invention also provides an efficient method of producing memory devices with the selection element in the same layer as one of the control lines.

    摘要翻译： 本发明有利于通过减少实现半导体存储器件所需的层数来制造半导体存储器组件。 本发明提供了一种选择元件，其形成在与控制线之一（例如字线和位线之一）相同的层中。 在本发明的一个实施例中，二极管被实现为与控制线之一在同一层内的选择元件。 生产作为字线和位线之一的同一层内的选择元件可减少与垂直堆叠相关的问题，提高了设备​​产量并降低了相关生产成本。 本发明还提供了一种生产存储器件的有效方法，其中选择元件与控制线之一在同一层中。

    System and method for processing an organic memory cell
    4.
    发明授权
    System and method for processing an organic memory cell 有权
    用于处理有机存储单元的系统和方法

    公开(公告)号：US07632706B2

    公开(公告)日：2009-12-15

    申请号：US11256558

    申请日：2005-10-21

    申请人： Nicolay F. Yudanov ,  Igor Sokolik ,  Richard P. Kingsborough ,  William G. Leonard ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Minh Van Ngo

    发明人： Nicolay F. Yudanov ,  Igor Sokolik ,  Richard P. Kingsborough ,  William G. Leonard ,  Suzette K. Pangrle ,  Nicholas H. Tripsas ,  Minh Van Ngo

    IPC分类号： H01L51/40

    CPC分类号： H01L51/001 ,  C23C16/54 ,  H01J2237/3321 ,  H01L27/285

    摘要： A system and method are disclosed for processing an organic memory cell. An exemplary system can employ an enclosed processing chamber, a passive layer formation component operative to form a passive layer on a first electrode, and an organic semiconductor layer formation component operative to form an organic semiconductor layer on the passive layer. A wafer substrate is not needed to transfer from a passive layer formation system to an organic semiconductor layer formation system. The passive layer is not exposed to air after formation of the passive layer and before formation of the organic semiconductor layer. As a result, conductive impurities caused by the exposure to air do not occur in the thin film layer, thus improving productivity, quality, and reliability of organic memory devices. The system can further employ a second electrode formation component operative to form a second electrode on the organic semiconductor layer.

    摘要翻译： 公开了一种用于处理有机存储单元的系统和方法。 示例性系统可以采用封闭的处理室，可操作以在第一电极上形成钝化层的无源层形成部件和可操作地在被动层上形成有机半导体层的有机半导体层形成部件。 晶片衬底不需要从钝化层形成系统转移到有机半导体层形成系统。 钝化层在形成无源层之后并且在形成有机半导体层之前不暴露于空气。 结果，在薄膜层中不会发生由暴露于空气引起的导电杂质，从而提高了有机存储器件的生产率，质量和可靠性。 该系统可以进一步采用可在有机半导体层上形成第二电极的第二电极形成部件。

    Systems and methods for a memory and/or selection element formed within a recess in a metal line
    5.
    发明授权
    Systems and methods for a memory and/or selection element formed within a recess in a metal line 有权
    用于存储和/或选择元件的系统和方法，其形成在金属线中的凹槽内

    公开(公告)号：US07199416B1

    公开(公告)日：2007-04-03

    申请号：US10985172

    申请日：2004-11-10

    申请人： Nicholas H. Tripsas ,  Minh Tran ,  Jeffrey Shields

    发明人： Nicholas H. Tripsas ,  Minh Tran ,  Jeffrey Shields

    IPC分类号： H01L27/108 ,  H01L23/58

    CPC分类号： H01L27/1021 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The subject invention provides systems and methodologies for fabrication of memory and/or selection (e.g., diodes) elements in a recession in a semiconductor layer. In particular, a trench of varying width is created in the semiconductor layer by employing various etching techniques. A metal film can be deposited in the trench according to a desired deposition thickness in order to seam close a narrow portion of the trench while form a dimple in a wide portion of the trench. The trench, after metal film deposition, exhibits a depression in wider trench portions relative to narrow trench portions. The depression can be utilized by placing one or more memory or selection layers in the depression, and a via can be formed over a portion of the trench to form an interconnect.

    摘要翻译： 本发明提供了用于制造半导体层中的凹陷中的存储器和/或选择（例如，二极管）元件的系统和方法。 特别地，通过采用各种蚀刻技术在半导体层中产生不同宽度的沟槽。 可以根据期望的沉积厚度在沟槽中沉积金属膜，以便在沟槽的宽部分形成凹坑的同时缝合沟槽的窄部分。 在金属膜沉积之后，沟槽相对于窄沟槽部分在较宽的沟槽部分中呈凹陷。 可以通过将一个或多个存储器或选择层放置在凹陷中来利用凹陷，并且可以在沟槽的一部分上形成通孔以形成互连。

    Memory device with a selection element and a control line in a substantially similar layer
    7.
    发明授权
    Memory device with a selection element and a control line in a substantially similar layer 有权
    具有选择元件和控制线的存储器件在基本相似的层中

    公开(公告)号：US07696017B1

    公开(公告)日：2010-04-13

    申请号：US12141180

    申请日：2008-06-18

    申请人： Nicholas H. Tripsas ,  Suzette Paugrle

    发明人： Nicholas H. Tripsas ,  Suzette Paugrle

    IPC分类号： H01L21/82

    CPC分类号： H01L27/1021 ,  H01L27/101

    摘要： The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wordline and bitline). In one embodiment of the invention, a diode is implemented as the selection element within the same layer as one of the control lines. Production of the selection element within the same layer as one of the wordline and bitline reduces problems associated with vertical stacking, increases device yield and reduces related production costs. The invention also provides an efficient method of producing memory devices with the selection element in the same layer as one of the control lines.

    摘要翻译： 本发明有利于通过减少实现半导体存储器件所需的层数来制造半导体存储器组件。 本发明提供了一种选择元件，其形成在与控制线之一（例如字线和位线之一）相同的层中。 在本发明的一个实施例中，二极管被实现为与控制线之一在同一层内的选择元件。 生产作为字线和位线之一的同一层内的选择元件可减少与垂直堆叠相关的问题，提高了设备​​产量并降低了相关生产成本。 本发明还提供了一种生产存储器件的有效方法，其中选择元件与控制线之一在同一层中。

    Methods and systems for memory devices
    8.
    发明申请
    Methods and systems for memory devices 有权
    存储器件的方法和系统

    公开(公告)号：US20080175054A1

    公开(公告)日：2008-07-24

    申请号：US11724774

    申请日：2007-03-16

    申请人： Bryan William Hancock ,  Nicholas H. Tripsas ,  Richard C. Blish

    发明人： Bryan William Hancock ,  Nicholas H. Tripsas ,  Richard C. Blish

    IPC分类号： G11C16/06 ,  G11C11/34 ,  G11C29/00 ,  G11C7/00 ,  G11C16/04

    CPC分类号： G11C16/3404 ,  G11C11/5671 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3431 ,  G11C2029/0411

    摘要： One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a different multi-bit value. If the threshold voltage of the cell has drifted outside of the number of allowable voltage states, then the cell is recovered by adjusting at least one voltage boundary of at least one of the number of allowable voltage states.

    摘要翻译： 本发明的一个实施例涉及一种用于刷新非易失性存储器阵列的方法。 在该方法中，分析多位存储单元的阈值电压以确定其是否漂移在许多允许电压窗口之外，其中每个可允许电压窗对应于不同的多位值。 如果电池的阈值电压漂移在容许电压状态数之外，则通过调节至少一个容许电压状态数量的至少一个电压边界来恢复电池。

    Planar polymer memory device
    9.
    发明授权
    Planar polymer memory device 有权
    平面聚合物记忆装置

    公开(公告)号：US06977389B2

    公开(公告)日：2005-12-20

    申请号：US10452877

    申请日：2003-06-02

    申请人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Uzodinma Okoroanyanwu ,  Suzette K. Pangrle

    发明人： Nicholas H. Tripsas ,  Matthew S. Buynoski ,  Uzodinma Okoroanyanwu ,  Suzette K. Pangrle

    IPC分类号： G11C11/56 ,  G11C13/02 ,  H01L27/115 ,  H01L27/24 ,  H01L27/28 ,  H01L35/24

    CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C11/5664 ,  G11C13/0016 ,  H01L27/28 ,  H01L51/0575

    摘要： The present invention provides a planar polymer memory device that can operate as a non-volatile memory device. A planar polymer memory device can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and dielectric separate the electrodes. The method for forming a planar polymer memory device comprises at least one of forming a first electrode with an associated plug, forming a second electrode, forming a passive layer over the extension, depositing an organic polymer and patterning the organic polymer. The method affords integration of a planar polymer memory device into a semiconductor fabrication process. A thin film diode (TFD) can further be employed with a planar polymer memory device to facilitate programming. The TFD can be formed between the first electrode and the selectively conductive medium or the second electrode and the selectively conductive medium.

    摘要翻译： 本发明提供一种能够作为非易失性存储器件操作的平面聚合物存储器件。 平面聚合物存储器件可以形成有两个或更多个电极和与一个电极相关联的电极延伸，其中选择性导电的介质和电介质分离电极。 用于形成平面聚合物记忆装置的方法包括以下步骤中的至少一种：形成具有相关塞子的第一电极，形成第二电极，在延伸部分上形成钝化层，沉积有机聚合物和图案化有机聚合物。 该方法将平面聚合物存储器件集成到半导体制造工艺中。 还可以使用薄膜二极管（TFD）与平面聚合物存储器件来促进编程。 可以在第一电极和选择性导电介质或第二电极和选择性导电介质之间形成TFD。

    Method(s) facilitating formation of memory cell(s) and patterned conductive
    10.
    发明授权
    Method(s) facilitating formation of memory cell(s) and patterned conductive 失效
    促进形成记忆体和图案化的导电聚合物膜的方法

    公开(公告)号：US06753247B1

    公开(公告)日：2004-06-22

    申请号：US10285183

    申请日：2002-10-31

    申请人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

    发明人： Uzodinma Okoroanyanwu ,  Suzette K. Pangrle ,  Matthew S. Buynoski ,  Nicholas H. Tripsas ,  Mark S. Chang ,  Ramkumar Subramanian ,  Angela T. Hui

    IPC分类号： H01L214763

    CPC分类号： G11C13/0014 ,  B82Y10/00 ,  G11C13/0016 ,  H01L27/285

    摘要： A methodology for forming a memory cell is disclosed, wherein an organic polymer layer is formed over a conductive layer and an electrode layer is formed over the organic polymer layer. A first via is etched into the electrode and organic polymer layers, and a dielectric material is applied over the stack to at least fill in the first via. A second via is then etched into the dielectric material so as to expose and make the electrode layer available as a top electrode. A wordline is then formed over the dielectric material such that the top electrode is connected to the wordline by way of the second via. A memory device formed in accordance with the disclosed methodology includes a top electrode formed over an organic polymer layer, a conductive layer under the organic polymer layer, a via defined by a dielectric material and located above the top electrode, and a wordline formed over the dielectric material such that the top electrode is connected to the wordline by way of the via.

    摘要翻译： 公开了一种用于形成存储单元的方法，其中在导电层上形成有机聚合物层，并且在有机聚合物层上形成电极层。 将第一通孔蚀刻到电极和有机聚合物层中，并且将电介质材料施加到堆叠上以至少填充在第一通孔中。 然后将第二通道蚀刻到电介质材料中，以暴露并使电极层可用作顶部电极。 然后在电介质材料上形成字线，使得顶部电极通过第二通孔连接到字线。 根据所公开的方法形成的存储器件包括形成在有机聚合物层上的顶部电极，有机聚合物层下面的导电层，由电介质材料限定并位于顶部电极之上的通孔，以及形成在上部电极上的字线 电介质材料，使得顶部电极通过通孔连接到字线。