公开(公告)号：US5019524A

公开(公告)日：1991-05-28

申请号：US401506

申请日：1989-08-30

申请人： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushiro Kusano ,  Masayoshi Kobayashi ,  Susumu Takahashi

发明人： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushiro Kusano ,  Masayoshi Kobayashi ,  Susumu Takahashi

IPC分类号： H01L29/205 ,  H01L21/331 ,  H01L29/10 ,  H01L29/73 ,  H01L29/737

CPC分类号： H01L29/66318 ,  H01L29/1004 ,  H01L29/7371 ,  Y10S148/01 ,  Y10S148/072 ,  Y10S148/084

摘要： Disclosed is a semiconductor device including a heterojunction bipolar transistor in which the front surface of a base layer and the surface of an emitter-base junction are covered with a high-resistivity layer of compound semiconductor containing at least one constituent element common to an emitter layer and the base layer.

公开(公告)号：US4979009A

公开(公告)日：1990-12-18

申请号：US415708

申请日：1989-09-29

申请人： Chushiro Kusano ,  Tomonori Tanoue ,  Katsuhiko Mitani

发明人： Chushiro Kusano ,  Tomonori Tanoue ,  Katsuhiko Mitani

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737

CPC分类号： H01L29/7371

摘要： 2A heterojunction bipolar transistor is disclosed in which a region of a base layer which extends in the vicinity of the interface between the base layer and an emitter layer is doped with an impurity at a higher concentration than that in the inside of the base layer to thereby form a built-in field by which carriers injected from the emitter are caused to drift to the inside of the base layer. In the transistor having this structure, the current gain does not depend on the emitter area, and it is possible to obtain a large current gain with a small emitter area.

摘要翻译： 2A公开了其中在基极层和发射极层之间的界面附近延伸的基极层的区域以比基底层内侧的浓度更高的浓度掺杂杂质的异质结双极晶体管，由此 形成内置的场，通过该场，使从发射器注入的载流子漂移到基层的内部。 在具有这种结构的晶体管中，电流增益不取决于发射极面积，并且可以获得具有小发射极面积的大电流增益。

公开(公告)号：US4983532A

公开(公告)日：1991-01-08

申请号：US286710

申请日：1988-12-20

申请人： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi ,  Masayoshi Saito ,  Hiroshi Miyazaki ,  Fumio Murai

发明人： Katsuhiko Mitani ,  Tomonori Tanoue ,  Chushirou Kusano ,  Susumu Takahashi ,  Masayoshi Saito ,  Hiroshi Miyazaki ,  Fumio Murai

IPC分类号： H01L29/205 ,  H01L21/331 ,  H01L29/73 ,  H01L29/737

CPC分类号： H01L29/66318 ,  Y10S148/01 ,  Y10S148/011 ,  Y10S148/072 ,  Y10S148/10

摘要： Microfabrication and large scale integration of a device can be realized by using a planar heterojunction bipolar transistor formed by a process comprising successively growing semiconductor layers serving as a subcollector, a collector, a base, and an emitter, respectively, through epitaxial growth on a compound semiconductor substrate in such a manner that at least one of the emitter junction and collector junction is a heterojunction, wherein a collector drawing-out metal layer is formed by the selective CVD method.

摘要翻译： 可以通过使用通过包括通过在化合物上的外延生长分别连续生长用作子集电极，集电极，基极和发射极的半导体层的工艺形成的平面异质结双极晶体管来实现器件的微结构和大规模集成 半导体衬底，其中发射极结和集电极结中的至少一个是异质结，其中通过选择性CVD法形成集电体引出金属层。

公开(公告)号：US5258631A

公开(公告)日：1993-11-02

申请号：US884878

申请日：1992-05-18

申请人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

发明人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

IPC分类号： H01L21/18 ,  H01L21/285 ,  H01L21/331 ,  H01L21/335 ,  H01L27/06 ,  H01L29/737 ,  H01L29/778 ,  H01L29/06 ,  H01L29/167 ,  H01L29/30 ,  H01L31/072

CPC分类号： H01L29/66318 ,  H01L21/182 ,  H01L21/28587 ,  H01L27/0605 ,  H01L29/66462 ,  H01L29/7373 ,  H01L29/7787

摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by introduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.

摘要翻译： 本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。 前者通过应用其源极和漏极区域的形成来制造通过引入杂质例如通过离子注入引起异质结的紊乱的技术或通过形成由 选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。 后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。 这些半导体器件可以降低源极栅极电阻和寄生基极电阻。 本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

公开(公告)号：US5381027A

公开(公告)日：1995-01-10

申请号：US134622

申请日：1993-10-12

申请人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

发明人： Toshiyuki Usagawa ,  Kenji Hiruma ,  Masahiko Kawata ,  Shigeo Goto ,  Katsuhiko Mitani ,  Masao Yamane ,  Susumu Takahashi ,  Tomonori Tanoue ,  Yoshinori Imamura

IPC分类号： H01L21/18 ,  H01L21/285 ,  H01L21/331 ,  H01L21/335 ,  H01L27/06 ,  H01L29/737 ,  H01L29/778 ,  H01L29/804 ,  H01L29/784

CPC分类号： H01L29/66318 ,  H01L21/182 ,  H01L21/28587 ,  H01L27/0605 ,  H01L29/66462 ,  H01L29/7373 ,  H01L29/7787

摘要： This invention discloses a heterojunction type field effect transistor such as 2DEG-FET and a heterojunction type bipolar transistor such as 2DEG-HBT. The former is fabricated by applying to the formation of its source and drain regions a technique which causes the disorder of the heterojunction by intoduction of an impurity such as by ion implantation or a technique which causes the disorder of the heterojunction by forming a film made of at least one kind of material selected from insulators, metals and semiconductors which have a different linear coefficient of thermal expansion from that of the material of a semiconductor substrate on the heterojunction semiconductor region which is to be disordered. The latter is fabricated by applying either of the techniques described above to a base ohmic contact region. These semiconductor devices can reduce the source-gate resistance and the parasitic base resistance. The invention discloses also the structure of the ohmic contact layer which has a trench on the surface thereof and is particularly effective for reducing the source-gate parasitic resistance.

摘要翻译： 本发明公开了一种异质结型场效应晶体管，例如2DEG-FET和异质结型双极晶体管，例如2DEG-HBT。 前者通过应用于其源极和漏极区域的形成来制造通过诸如通过离子注入引起杂质的异质结的紊乱或通过形成由 选自绝缘体，金属和半导体的至少一种材料，其具有不同于待混杂的异质结半导体区域上的半导体衬底的材料的线性热膨胀系数。 后者通过将上述技术中的任一种应用于基极欧姆接触区域来制造。 这些半导体器件可以降低源极栅极电阻和寄生基极电阻。 本发明还公开了欧姆接触层的结构，其在其表面上具有沟槽，并且对于减小源极寄生电阻特别有效。

公开(公告)号：US5017517A

公开(公告)日：1991-05-21

申请号：US518035

申请日：1990-05-02

申请人： Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chushirou Kusano ,  Hiroshi Masuda ,  Katsuhiko Mitani

发明人： Kazuhiro Mochizuki ,  Tomonori Tanoue ,  Chushirou Kusano ,  Hiroshi Masuda ,  Katsuhiko Mitani

IPC分类号： H01L29/73 ,  H01L21/20 ,  H01L21/28 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L29/80

CPC分类号： H01L29/66318 ,  H01L21/02395 ,  H01L21/02463 ,  H01L21/02491 ,  H01L21/02546 ,  H01L21/02639 ,  H01L21/28 ,  Y10S148/005 ,  Y10S148/011 ,  Y10S148/026 ,  Y10S438/976

摘要： A method for fabricating a semiconductor device comprises the steps of forming the first semiconductor layer on a semiconductor substrate, forming a surface protection layer of antimony (Sb) or the material having Sb as its main component, executing the other steps necessary for the fabrication of the semiconductor device, removing the surface protection layer, and forming, on the first semiconductor layer thus exposed, the second semiconductor layer.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：在半导体衬底上形成第一半导体层，形成锑（Sb）的表面保护层或具有Sb的材料作为其主要成分，执行制造所需的其它步骤 半导体器件，去除表面保护层，并且在由此暴露的第一半导体层上形成第二半导体层。

公开(公告)号：US5296733A

公开(公告)日：1994-03-22

申请号：US615381

申请日：1990-11-19

申请人： Chushiroh Kusano ,  Hiroshi Masuda ,  Katsuhiko Mitani ,  Kazuhiro Mochizuki ,  Masaru Miyazaki ,  Masahiko Kawata ,  Susumu Takahashi

发明人： Chushiroh Kusano ,  Hiroshi Masuda ,  Katsuhiko Mitani ,  Kazuhiro Mochizuki ,  Masaru Miyazaki ,  Masahiko Kawata ,  Susumu Takahashi

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L29/205 ,  H01L29/737 ,  H01L29/72 ,  H01L29/06

CPC分类号： H01L29/7371

摘要： A hetero junction bipolar transistor provides a contact area an area between an emitter (or collector) electrode and a wiring formed on the electrode that is larger than that of the emitter (or collector). A variation in voltage applied to an emitter (or collector)-base junctions is prevented and a stable operation of the transistor is attained. In addition, when an etching operation is carried out, an insulation film is formed on a side part of a mask. A patterning of the emitter (or collector) is then carried out and thus an emitter (or collector) having a size approximate to that of the mask is formed.

摘要翻译： 异质结双极晶体管提供接触区域，其在发射极（或集电极）电极和形成在电极上的布线之间的面积大于发射极（或集电极）的面积。 防止施加到发射极（或集电极） - 基极结的电压变化，并且获得晶体管的稳定操作。 另外，当进行蚀刻操作时，在掩模的侧面上形成绝缘膜。 然后执行发射极（或集电极）的图案化，因此形成具有接近于掩模的尺寸的发射极（或集电极）。

公开(公告)号：US5668402A

公开(公告)日：1997-09-16

申请号：US66635

申请日：1993-05-24

申请人： Kazuhiro Mochizuki ,  Shigeo Goto ,  Chushirou Kusano ,  Masahiko Kawata ,  Hiroshi Masuda ,  Katsuhiko Mitani ,  Susumu Takahashi

发明人： Kazuhiro Mochizuki ,  Shigeo Goto ,  Chushirou Kusano ,  Masahiko Kawata ,  Hiroshi Masuda ,  Katsuhiko Mitani ,  Susumu Takahashi

IPC分类号： H01L29/73 ,  A61F7/02 ,  H01L21/20 ,  H01L21/331 ,  H01L21/338 ,  H01L29/04 ,  H01L29/205 ,  H01L29/737 ,  H01L29/812

CPC分类号： H01L29/045 ,  H01L21/02395 ,  H01L21/02433 ,  H01L21/02463 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02609 ,  A61F2007/0265

摘要： A semiconductor device comprises a semiconductor substrate formed by a first single crystalline semiconductor material and semiconductor layers formed on the semiconductor substrate by a second single crystalline semiconductor material doped with an element which can easily surface segregate. The surface of the semiconductor substrate is formed of a crystalline plane substantially equivalent to a facet plane which is formed on the surface of the second single crystalline semiconductor material if the second single crystalline semiconductor material is epitaxially grown with being doped with the element on a (100) plane of the first single crystalline semiconductor material.

摘要翻译： 半导体器件包括由第一单晶半导体材料形成的半导体衬底和通过掺杂有易于表面分离的元件的第二单晶半导体材料形成在半导体衬底上的半导体层。 半导体衬底的表面由与第二单晶半导体材料的表面上形成的小平面基本相同的晶面形成，如果第二单晶半导体材料被外延生长，在第 100）平面的第一单晶半导体材料。

公开(公告)号：US20060183057A1

公开(公告)日：2006-08-17

申请号：US11055623

申请日：2005-02-11

申请人： Katsuhiko Mitani ,  Hiroshi Fukuda

发明人： Katsuhiko Mitani ,  Hiroshi Fukuda

IPC分类号： G03F7/00

CPC分类号： G03F7/2051 ,  G03F7/70383

摘要： Formation of a photomask in the conventional art requires significant cost and time. The invention provides a patterning method of forming a desired latent image pattern by irradiating a resist film formed on a substrate with focused light beam. The method comprising adjusting intensity of the focused light beam or size thereof on the resist film depending on a design of the pattern to irradiate the resist film, thereby achieving a desired pattern with reasonable cost and time.

摘要翻译： 在传统技术中形成光掩模需要大量的成本和时间。 本发明提供一种通过用聚焦光束照射形成在基板上的抗蚀剂膜来形成期望的潜像图案的图案化方法。 该方法包括根据用于照射抗蚀剂膜的图案的设计来调整抗蚀剂膜上的聚焦光束的强度或其尺寸，从而以合理的成本和时间实现期望的图案。

公开(公告)号：US20050082006A1

公开(公告)日：2005-04-21

申请号：US10985052

申请日：2004-11-10

申请人： Tetsunori Kaji ,  Shinichi Tachi ,  Toru Otsubo ,  Katsuya Watanabe ,  Katsuhiko Mitani ,  Junichi Tanaka

发明人： Tetsunori Kaji ,  Shinichi Tachi ,  Toru Otsubo ,  Katsuya Watanabe ,  Katsuhiko Mitani ,  Junichi Tanaka

IPC分类号： H01J37/32 ,  H01L21/00 ,  C23F1/00

CPC分类号： H01J37/32082 ,  H01J37/32623 ,  H01J37/32678 ,  H01L21/67069

摘要： A plasma processing apparatus includes a vacuum processing chamber having a pair of opposing electrodes for plasma generation, one electrode serving as a sample table for a sample including an insulator film. An electrostatic adsorption film is arranged at the sample table electrode to supply a thermal conductive gas between the film and the sample rear surface. A pressure reducing element is also provided. In addition, arrangements are provided to set a gas pressure within said vacuum processing chamber to 0.5 to 4.0 Pa and to apply a high frequency power of 30 MHz to 200 MHz between the electrodes. An electrode cover s disposed at the other electrode, and a clearance between the electrodes is 30 mm to 100 mm. The electrode cover includes fine apertures to introduce a fluorine-containing etching gas, and a power supply accelerates ions in the plasma

摘要翻译： 等离子体处理装置包括具有一对用于等离子体产生的相对电极的真空处理室，一个用作用于包括绝缘膜的样品的样品台的电极。 在样品台电极处设置静电吸附膜，以在膜和样品后表面之间提供导热气体。 还提供减压元件。 此外，提供了将所述真空处理室内的气体压力设定为0.5〜4.0Pa并在电极之间施加30MHz〜200MHz的高频功率的结构。 设置在另一个电极处的电极盖和电极之间的间隙为30mm至100mm。 电极盖包括用于引入含氟蚀刻气体的细孔，并且电源加速等离子体中的离子