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30 条记录 (耗时 0.009 秒)

    Process for fabricating a semiconductor device using dual planarization layers
    1.
    发明授权
    Process for fabricating a semiconductor device using dual planarization layers 失效
    使用双平面化层制造半导体器件的工艺

    公开(公告)号：US5459096A

    公开(公告)日：1995-10-17

    申请号：US270545

    申请日：1994-07-05

    申请人： Suresh Venkatesan ,  Stephen Poon

    发明人： Suresh Venkatesan ,  Stephen Poon

    IPC分类号： H01L21/3105 ,  H01L21/302

    CPC分类号： H01L21/31053 ,  H01L21/31055 ,  Y10S148/005 ,  Y10S438/97

    摘要： An improved planarization process includes the steps of forming recessed regions (38) and elevated regions (34) in a semiconductor substrate (30). The substrate is oxidized to form an oxide liner (39) overlying the recessed regions, and a fill material (40) is deposited to overlie the substrate (30) filling the recessed regions (38). An etching process is used to remove portions of the fill material (40) and to expose portions of a first planarization layer (44) overlying the elevated regions (34) of the substrate (30). The fill material is etched and a second planarization layer (46) is deposited to overlie dielectric portions (42), and portions (44) of first planarization layer (32) exposed by the etching process. A chemical-mechanical-polishing process is then carried out to form a planar surface (47), and remaining portions of the planarization layers and fill material are removed.

    摘要翻译： 改进的平面化处理包括在半导体衬底（30）中形成凹陷区域（38）和升高区域（34）的步骤。 衬底被氧化以形成覆盖在凹陷区域上的氧化物衬垫（39），并且沉积填充材料（40）以覆盖填充凹陷区域（38）的衬底（30）。 蚀刻工艺用于去除填充材料（40）的部分并暴露覆盖衬底（30）的升高区域（34）的第一平坦化层（44）的部分。 蚀刻填充材料，并且沉积第二平坦化层（46）以覆盖介电部分（42）和通过蚀刻工艺暴露的第一平坦化层（32）的部分（44）。 然后进行化学机械抛光工艺以形成平坦表面（47），并且除去平坦化层和填充材料的剩余部分。

    Vapor phase epitaxial deposition process for forming superlattice structure
    2.
    发明授权
    Vapor phase epitaxial deposition process for forming superlattice structure 失效
    形成超结构的蒸气相外延沉积工艺

    公开(公告)号：US3721583A

    公开(公告)日：1973-03-20

    申请号：US3721583D

    申请日：1970-12-08

    申请人： IBM

    发明人： BLAKESLEE A

    IPC分类号： H01L21/205 ,  B44D1/18

    CPC分类号： H01L21/02392 ,  H01L21/02395 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/0262 ,  Y10S117/902 ,  Y10S148/005 ,  Y10S148/056 ,  Y10S148/065 ,  Y10S148/067 ,  Y10S148/072 ,  Y10S148/129 ,  Y10S438/936

    摘要： A VAPOR PHASE EPITAXIAL PROCESS FOR FORMING A SUPERLATTICE STRUCTURE COMPRISING ALTERNATE LAYERS OF DIFFERENT SEMICONDUCTOR MATERIALS ON A SUBSTRATE. IN THE SUPERLATTICE, THE PROPORTION OF ONE COMPONENT IS CAUSED TO PERIODICALLY VARY FROM A DESIRED MAXIMUM TO A DESIRED MINIMUM OVER AN EXTREMELY SMALL PERIOD. FOR AN N COMPONENT SYSTEM, THIS IS ACCOMPLISHED BY FORMING A STREAM COMPRISING N-1 COOPONENTS AND INJECTING PULSES OF THE NTH COMPONENT IN A CARRIER GAS SEPARATED BY PULSES OF CARRIER GAS INTO THE N-1 COMPONENT STREAM, TO THEREBY PROVIDE AT THE SUBSTRATE ALTERNATE, DISCRETE BURSTS OF GAS COMPRISING N COMPONENTS AND N-1 COMPONENTS, RESPECTIVELY. BY CRITICALLY CONTROLLING DIFFUSION OF ADJACENT PULSES AND BURSTS, THE PROPORTION OF THE NTH COMPONENT IN THE SUPERLATTICE STRUCTURE CAN BE VARIED FROM A MAXIMUM TO A MINUMUM WITHIN AN EXTREMELY SMALL PERIOD. HIGH TEMPERATURE, VAPOR PHASE EPITAXIAL DEPOSITION APPARATUS FOR DEPOSITING SUCH A REPETITIVE SUPERLATTICE STRUCTURE: BASICALLY A PULSING CHAMBER TO RECEIVE THE N-1 COMPONENT STREAM; PULSING MEANS TO PERIODICALLY PULSE THE NTH COMPONENT INTO THE N-1 COMPONENT STREAM, WHEREBY THE BURSTS DESCRIBED ABOVE ARE FORMED; AND DEPOSITION MEANS CONTAINING A SUBSTRATE TO RECEIVE SAID BURSTS FOR THE FORMATION OF SAD SUPERLATTICE. ALL ELEMENTS ARE CORRELATED TO PERMIT DIFFUSION TO BE CRITICALLY CONTROLLED.

    D R A W I N G

    MBE growth technology for high quality strained III-V layers
    5.
    发明授权
    MBE growth technology for high quality strained III-V layers 失效
    用于高品质应变III-V层的MBE增长技术

    公开(公告)号：US5091335A

    公开(公告)日：1992-02-25

    申请号：US506137

    申请日：1990-03-30

    申请人： Frank J. Grunthaner ,  John K. Liu ,  Bruce R. Hancock

    发明人： Frank J. Grunthaner ,  John K. Liu ,  Bruce R. Hancock

    IPC分类号： H01L21/20 ,  H01L21/203

    CPC分类号： H01L21/02381 ,  H01L21/02395 ,  H01L21/02398 ,  H01L21/02463 ,  H01L21/02507 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/02631 ,  Y10S148/005 ,  Y10S148/018 ,  Y10S438/938

    摘要： III-V films are grown on large automatically perfect terraces of III-V substrates which have a different lattice constant, with temperature and Group II and V arrival rates chosen to give a Group III element stable surface. The growth is pulsed to inhibit Group III metal accumulation to low temperature, and to permit the film to relax to equilibrium. The method of the invention 1) minimizes starting step density on sample surface; 2) deposits InAs and GaAs using an interrupted growth mode (0.25 to 2 mono-layers at a time); 3) maintains the instantaneous surface stoichiometry during growth (As-stable for GaAs, In-stable for InAs); and 4) uses time-resolved RHEED to achieve aspects (1)-14 (3).

    摘要翻译： III-V膜生长在具有不同晶格常数的III-V衬底的大型自动完美梯田上，其温度选择为II族和V族到达率，以提供III族元素稳定的表面。 脉冲生长以抑制III族金属积聚到低温，并允许膜松弛至平衡。 本发明的方法1）最小化样品表面的起始步骤密度; 2）使用中断生长模式沉积InAs和GaAs（每次0.25至2个单层）; 3）在生长过程中保持瞬时表面化学计量（GaAs稳定，InAs稳定）; 和4）使用时间分辨的RHEED来实现方面（1）-14（3）。

    Ultra-thin semiconductor membranes
    10.
    发明授权
    Ultra-thin semiconductor membranes 失效
    超薄半导体膜

    公开(公告)号：US4952446A

    公开(公告)日：1990-08-28

    申请号：US284822

    申请日：1988-12-14

    申请人： Kevin C. Lee ,  Charles A. Lee ,  John Silcox

    发明人： Kevin C. Lee ,  Charles A. Lee ,  John Silcox

    IPC分类号： H01L21/265 ,  H01L21/3063 ,  H01L21/324 ,  H01L21/425 ,  H01L21/465 ,  H01L21/477

    CPC分类号： H01L21/26506 ,  H01L21/2654 ,  H01L21/3063 ,  H01L21/30635 ,  H01L21/324 ,  H01L21/3245 ,  H01L21/425 ,  H01L21/465 ,  H01L21/477 ,  Y10S148/003 ,  Y10S148/005 ,  Y10S148/042 ,  Y10S148/056 ,  Y10S148/058 ,  Y10S148/064 ,  Y10S148/065 ,  Y10S148/083 ,  Y10S148/119 ,  Y10S148/135 ,  Y10S148/90 ,  Y10S438/924 ,  Y10S438/977 ,  Y10T428/261 ,  Y10T428/266 ,  Y10T428/31 ,  Y10T428/315

    摘要： This invention relates to ultra-thin semiconductor films which can be in the submicron range formed from semiconductor materials such as silicon, germanium and gallium arsenide. The films are formed by creating a thin slightly damaged surface on the polished reverse side of a film (e.g., a wafer) of the semiconductor by low dose ion implantation and then etching the semiconductor material on the front side of the film to remove the semiconductor material down to the ion implanted damaged layer. While the implanted ions can be chosen from functionally desirable ions which upon annealing remain in the film to alter the original electrical characteristics, the implanted ions can also be chosen so that upon annealing, the resultant ultra-thin semiconductor film has the same electrical characteristics as the original semiconductor material.The ion implantation changes the etching characteristics of the ion implanted layer. Thus, when the partially damaged semiconductor material is exposed to an etchant the etching rate in the damaged region is decreased by a factor of several thousand as compared to the undamaged semiconductor material.

    摘要翻译： 本发明涉及可以由诸如硅，锗和砷化镓的半导体材料形成的亚微米范围的超薄半导体膜。 通过低剂量离子注入在半导体的膜（例如，晶片）的抛光反面上形成薄的稍微损伤的表面，然后蚀刻膜前侧的半导体材料以除去半导体， 材料下降到离子植入损伤层。 虽然注入的离子可以从功能上需要的离子中选择，当退火保留在膜中以改变原始电特性时，也可以选择注入的离子，使得在退火时，所得的超薄半导体膜具有与 原来的半导体材料。 离子注入改变离子注入层的蚀刻特性。 因此，当部分损坏的半导体材料暴露于蚀刻剂时，与未损坏的半导体材料相比，损伤区域中的蚀刻速率降低了几千倍。