公开(公告)号：US5381032A

公开(公告)日：1995-01-10

申请号：US111964

申请日：1993-08-26

申请人： Yoshiko Kokawa ,  Tohru Koyama ,  Kenji Kusakabe ,  Katsuhiko Tamura ,  Yasuna Nakamura

发明人： Yoshiko Kokawa ,  Tohru Koyama ,  Kenji Kusakabe ,  Katsuhiko Tamura ,  Yasuna Nakamura

IPC分类号： H01L21/205 ,  H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/3205 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L23/48 ,  H01L23/52 ,  H01L29/04

CPC分类号： H01L21/26586 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/32055 ,  H01L29/4916

摘要： A semiconductor device without erroneous operation and deterioration of characteristics in a transistor even when an impurity region is formed in self-alignment by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. This semiconductor device includes a gate electrode formed of a polycrystal silicon layer 4b having the crystal orientation of the crystal grains arranged in a definite orientation. By implanting ions at a predetermined angle with respect to the crystallographic axis of the crystal grains of the polycrystal silicon layer 4b in forming a p.sup.+ impurity region 5 by ion implantation using the gate electrode as a mask, the channeling phenomenon where ions pass through the gate electrode is prevented. Therefore, generation of erroneous operation and deterioration of characteristics in a transistor are prevented in forming an impurity region in self-alignment by ion implantation using the gate electrode as a mask.

摘要翻译： 即使在通过使用栅电极作为掩模的离子注入来自对准地形成杂质区域的情况下，晶体管也不会发生误操作和特性劣化的半导体器件及其制造方法。 该半导体器件包括由具有以确定取向排列的晶粒的晶体取向的多晶硅层4b形成的栅电极。 通过使用栅极电极作为掩模通过离子注入形成p +杂质区域5时，相对于多晶硅层4b的晶粒的结晶轴以预定的角度注入离子，其中离子通过 防止栅电极。 因此，通过使用栅电极作为掩模，通过离子注入形成自对准中的杂质区域，防止了晶体管中错误操作的产生和特性劣化。

公开(公告)号：US5360756A

公开(公告)日：1994-11-01

申请号：US160717

申请日：1993-12-02

申请人： Katsuhiko Tamura

发明人： Katsuhiko Tamura

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/265

CPC分类号： H01L29/66825 ,  H01L29/7886 ,  H01L27/115 ,  Y10S438/91

摘要： According to a method of manufacturing a semiconductor device, a monocrystal silicon layer can be formed easily without adversely affecting semiconductor elements. In the method of manufacturing the semiconductor device, a first polysilicon layer is formed on a gate oxide film layer on a silicon substrate, and then a resist is formed on a predetermined region of the first polysilicon layer. Using the resist as a mask, anisotropic etching is effected to expose the surface of the silicon substrate. Thereby, it is not necessary to form the resist directly on the gate oxide film layer, as is done in the prior art, and it is possible to prevent impurity such as sodium or phosphorus in the resist from entering the gate oxide film layer. Consequently, it is possible to prevent a disadvantage such as change of a threshold voltage of a memory cell transistor, which may be caused by the entry of impurity.

摘要翻译： 根据半导体装置的制造方法，可以容易地形成单晶硅层，而不会对半导体元件产生不利影响。 在制造半导体器件的方法中，在硅衬底上的栅极氧化膜层上形成第一多晶硅层，然后在第一多晶硅层的预定区域上形成抗蚀剂。 使用抗蚀剂作为掩模，进行各向异性蚀刻以暴露硅衬底的表面。 因此，如现有技术那样，不需要在栅极氧化膜层上直接形成抗蚀剂，并且可以防止抗蚀剂中的钠或磷等杂质进入栅氧化膜层。 因此，可以防止由杂质的进入引起的存储单元晶体管的阈值电压的变化等缺陷。

公开(公告)号：US5338955A

公开(公告)日：1994-08-16

申请号：US6870

申请日：1993-01-21

申请人： Katsuhiko Tamura ,  Atsuko Kawai

发明人： Katsuhiko Tamura ,  Atsuko Kawai

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/68

CPC分类号： H01L27/10817

摘要： A DRAM providing a capacitor capacity sufficient for maintaining stable storage of data even if elements are further reduced in size in accordance with high density integration of semiconductor devices is disclosed. The DRAM has its capacitor upper electrode formed of an upper layer and a lower layer, and its capacitor lower electrode formed to surround the lower layer of the capacitor upper layer, and the upper layer of the capacitor upper layer formed to cover the upper surface and both sides of the capacitor lower electrode. Thus, a capacitor capacity is tremendously increased as compared to a conventional one in the same plane area as the conventional one.

摘要翻译： 公开了提供足够的电容器容量的DRAM，即使根据半导体器件的高密度集成，元件的尺寸进一步减小，也能够保持数据的稳定存储。 DRAM具有由上层和下层形成的电容器上电极，并且其电容器下电极形成为围绕电容器上层的下层，并且形成为覆盖上表面的电容器上层的上层， 电容器下电极两侧。 因此，与现有技术相同的平面区域中的电容器容量相比，电容器容量大大增加。

公开(公告)号：US5434813A

公开(公告)日：1995-07-18

申请号：US114274

申请日：1993-08-31

申请人： Katsuhiko Tamura ,  Yukari Imai ,  Naoko Otani

发明人： Katsuhiko Tamura ,  Yukari Imai ,  Naoko Otani

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01L27/10

CPC分类号： H01L29/66825 ,  H01L29/511 ,  H01L27/115 ,  Y10S438/981

摘要： A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.

摘要翻译： 半导体存储器件有效地防止了在数据写入和擦除操作中电子移动的区域上形成栅极鸟喙氧化物膜。 在半导体存储器件中，在漏极杂质扩散层和源极杂质扩散层上形成厚度大于第一栅极氧化物膜的氮化物膜以围绕第一栅极氧化物膜。 浮栅电极具有突出在氮化物膜上的相对端。

公开(公告)号：US4765963A

公开(公告)日：1988-08-23

申请号：US911354

申请日：1986-09-24

申请人： Yasukazu Mukogawa ,  Katsuhiko Tamura ,  Takaaki Fukumoto

发明人： Yasukazu Mukogawa ,  Katsuhiko Tamura ,  Takaaki Fukumoto

IPC分类号： G01N15/06 ,  G01N31/02 ,  G01N33/18 ,  G01N35/08

CPC分类号： G01N15/06 ,  G01N2015/0662 ,  Y10T436/117497

摘要： A sampled flow of water is extracted from a water conduit 1 carrying impure water by a sampling tube 2, the pressure at a point in the sampling tube is kept constant by a constant pressure maintaining valve 4, and the sampled water passed through a filter 7. The flow rate of sampled water passing through the filter 7 is measured by a flow meter 8. A value corresponding to the total amount or level of impurity in the sampled water is evaluated by an operation circuit 9 at a prescribed time interval, based on the time-dependent change in the result of measurement of the flow meter 8 and the total amount or level of impurities in pure water is thus measured indirectly.

摘要翻译： 从采样管2携带不纯水的水管道1抽取取样的水流，采样管中的一点处的压力通过恒压保持阀4保持恒定，并且取样的水通过过滤器7 通过流量计8测量通过过滤器7的取样水的流量。对应于取样水中的杂质总量或水平的值，由操作电路9以规定的时间间隔基于 因此间接地测量流量计8的测量结果的时间依赖性变化和纯水中杂质的总量或水平。

公开(公告)号：US5633184A

公开(公告)日：1997-05-27

申请号：US386367

申请日：1995-02-09

申请人： Katsuhiko Tamura ,  Yukari Imai ,  Naoko Otani

发明人： Katsuhiko Tamura ,  Yukari Imai ,  Naoko Otani

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792 ,  H01C21/8247 ,  H01C21/265

CPC分类号： H01L29/66825 ,  H01L29/511 ,  H01L27/115 ,  Y10S438/981

摘要： A semiconductor memory device effectively prevents formation of a gate bird's beak oxide film at a region through which electrons move in data writing and erasing operations. In the semiconductor memory device, nitride films having a thickness larger than that of a first gate oxide film are formed on a drain impurity diffusion layer and a source impurity diffusion layer to surround the first gate oxide film. A floating gate electrode has opposite ends protruded over the nitride films.

摘要翻译： 半导体存储器件有效地防止了在数据写入和擦除操作中电子移动的区域上形成栅极鸟喙氧化物膜。 在半导体存储器件中，在漏极杂质扩散层和源极杂质扩散层上形成厚度大于第一栅极氧化物膜的氮化物膜以围绕第一栅极氧化物膜。 浮栅电极具有突出在氮化物膜上的相对端。

公开(公告)号：US5221630A

公开(公告)日：1993-06-22

申请号：US961972

申请日：1992-10-16

申请人： Tohru Koyama ,  Katsuhiko Tamura ,  Yasuna Nakamura ,  Yoshiko Kokawa ,  Kenji Kusakabe

发明人： Tohru Koyama ,  Katsuhiko Tamura ,  Yasuna Nakamura ,  Yoshiko Kokawa ,  Kenji Kusakabe

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/49

CPC分类号： H01L29/66575 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/4925 ,  Y10S438/945

摘要： A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.

摘要翻译： 即使当通过使用栅极电极作为掩模的离子注入形成杂质区域时，半导体器件也不会加剧晶体管特性及其制造方法。 该半导体器件包括：由多晶硅层4形成的栅电极10，该多晶硅层4具有以预定方向排列的晶粒的晶体取向，以及形成在多晶硅层4上的单晶硅层5，晶体取向与 在多晶硅层4的沟道化现象中，通过离子注入形成杂质区6，可以防止B +离子通过到栅电极10下方的沟道现象，从而获得不具有形成晶体管特性的半导体器件加重 。

公开(公告)号：US5177569A

公开(公告)日：1993-01-05

申请号：US789722

申请日：1991-11-08

申请人： Tohru Koyama ,  Katsuhiko Tamura ,  Yasuna Nakamura ,  Yoshiko Kokawa ,  Kenji Kusakabe

发明人： Tohru Koyama ,  Katsuhiko Tamura ,  Yasuna Nakamura ,  Yoshiko Kokawa ,  Kenji Kusakabe

IPC分类号： H01L21/265 ,  H01L21/266 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/43 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66575 ,  H01L21/26586 ,  H01L21/266 ,  H01L21/28035 ,  H01L29/4925

摘要： A semiconductor device not aggravated in transistor characteristic even when an impurity region is formed by ion implantation using a gate electrode as a mask, and a method of manufacturing thereof are disclosed. The semiconductor device includes a gate electrode 10 implemented by a polycrystal silicon layer 4 having the crystal orientation of the crystal grains thereof arranged in a predetermined orientation, and a single crystal silicon layer 5 formed on the polycrystal silicon layer 4 having a crystal orientation identical to that of the polycrystal silicon layer 4. The channelling phenomenon in which B.sup.+ ions pass through to beneath the gate electrode 10 is prevented in forming an impurity region 6 by ion implantation to obtain a semiconductor device that does not have the characteristic of the formed transistor aggravated.

摘要翻译： 即使当通过使用栅极电极作为掩模的离子注入形成杂质区域时，半导体器件也不会加剧晶体管特性及其制造方法。 该半导体器件包括：由多晶硅层4形成的栅电极10，该多晶硅层4具有以预定方向排列的晶粒的晶体取向，以及形成在多晶硅层4上的单晶硅层5，晶体取向与 在多晶硅层4的沟道化现象中，通过离子注入形成杂质区6，可以防止B +离子通过到栅电极10下方的沟道现象，从而获得不具有形成晶体管特性的半导体器件加重 。

公开(公告)号：US4778584A

公开(公告)日：1988-10-18

申请号：US875089

申请日：1986-06-17

申请人： Noboru Inoue ,  Takaaki Fukumoto ,  Masaharu Hama ,  Katsuhiko Tamura ,  Kimihiko Okaue

发明人： Noboru Inoue ,  Takaaki Fukumoto ,  Masaharu Hama ,  Katsuhiko Tamura ,  Kimihiko Okaue

IPC分类号： B01D35/06 ,  B03C5/02 ,  C02F1/463

CPC分类号： B01D35/06 ,  B03C5/024 ,  C02F1/463

摘要： Disclosed is a liquid filter device for effectively eliminating impurities from liquid.Voltage is applied to liquid to break electrostatic coupling of liquid molecules and impurity molecules. The impurity molecules are electrostatically adsorbed by an electrode containing adsorbent having charges different in polarity from those of the impurity molecules.Voltage is applied to liquid to break electrostatic coupling of liquid molecules and impurity molecules. Adsorbent having charges different in polarity from those of the impurity molecules on its surface is provided between a pair of electrodes to electrostatically adsorb the impurity molecules. After the impurity molecules are electrostatically adsorbed, the liquid is filtrated by a filter.Voltage is applied to liquid to eliminate zeta potentials which are potential difference at electric double layers having charges different in polarity from those of impurity particles in interfaces between the impurity particles and the liquid. The impurity particles are electrostatically aggregated, and the liquid is filtrated by a filter.

摘要翻译： 公开了一种用于有效地消除液体中的杂质的液体过滤装置。 将电压施加到液体以破坏液体分子和杂质分子的静电耦合。 杂质分子由含有不同于杂质分子极性电荷的吸附剂的电极静电吸附。 将电压施加到液体以破坏液体分子和杂质分子的静电耦合。 具有与其表面上的杂质分子极性不同的电荷的吸附剂设置在一对电极之间以静电吸附杂质分子。 杂质分子被静电吸附后，用过滤器过滤液体。 将电压施加到液体以消除作为杂质粒子和液体之间的界面中杂质粒子的极性不同的电荷的双电层的电位差的ζ电位。 杂质颗粒被静电聚集，并通过过滤器过滤液体。