公开(公告)号：US20110180708A1

公开(公告)日：2011-07-28

申请号：US13081875

申请日：2011-04-07

申请人： Katsunori Hirano ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

发明人： Katsunori Hirano ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

IPC分类号： H01J37/28

CPC分类号： G01N23/2251 ,  H01J2237/221 ,  H01J2237/2817

摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

摘要翻译： 用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。 用任意方向的电子束扫描样品中要测试的区域。 作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。 通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够执行高速扫描控制的具有多种扫描类型的测试装置。

公开(公告)号：US20090072138A1

公开(公告)日：2009-03-19

申请号：US12173038

申请日：2008-07-15

申请人： Katsunori HIRANO ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

发明人： Katsunori HIRANO ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

IPC分类号： G01N23/00

CPC分类号： G01N23/2251 ,  H01J2237/221 ,  H01J2237/2817

摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

摘要翻译： 用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。 用任意方向的电子束扫描样品中要测试的区域。 作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。 通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够执行高速扫描控制的具有多种扫描类型的测试装置。

公开(公告)号：US08304726B2

公开(公告)日：2012-11-06

申请号：US13081875

申请日：2011-04-07

申请人： Katsunori Hirano ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

发明人： Katsunori Hirano ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

IPC分类号： H01J37/304

CPC分类号： G01N23/2251 ,  H01J2237/221 ,  H01J2237/2817

摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

摘要翻译： 用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。 用任意方向的电子束扫描样品中要测试的区域。 作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。 通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够执行高速扫描控制的具有多种扫描类型的测试装置。

公开(公告)号：US07952072B2

公开(公告)日：2011-05-31

申请号：US12173038

申请日：2008-07-15

申请人： Katsunori Hirano ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

发明人： Katsunori Hirano ,  Tadanobu Toba ,  Masahiro Ohashi ,  Masashi Wada

IPC分类号： H01J37/304

CPC分类号： G01N23/2251 ,  H01J2237/221 ,  H01J2237/2817

摘要： A scan control unit for generating two-dimensional coordinates for performing a scan with an electron beam of an electron scanning microscope is provided with first and second transforming units for transforming coordinates in the horizontal (X) direction and the vertical (V) direction. An area to be tested in a sample is scanned with an electron beam in an arbitrary direction. As the first and second transforming units, small-capacity transformation tables (LUTs) capable of operating at high speed in each of the horizontal (X) direction and the vertical (Y) direction are used. By also using a large-capacity transformation table (LUT) that stores coordinate transformation data corresponding to plural scan types, a test apparatus compatible with the plural scan types, having multiple functions, and capable of performing high-speed scan control is realized.

摘要翻译： 用于产生用电子扫描显微镜的电子束执行扫描的二维坐标的扫描控制单元设置有用于变换水平（X）方向和垂直（V）方向上的坐标的第一和第二变换单元。 用任意方向的电子束扫描样品中要测试的区域。 作为第一变换单元和第二变换单元，使用能够在水平（X）方向和垂直（Y）方向中的每一个中高速运转的小容量变换表（LUT）。 通过使用存储与多种扫描类型相对应的坐标变换数据的大容量变换表（LUT），实现具有多种功能，能够进行高速扫描控制的具有多种扫描类型的测试装置。

公开(公告)号：US07811546B2

公开(公告)日：2010-10-12

申请号：US11748398

申请日：2007-05-14

申请人： Hisakatsu Kato ,  Masashi Wada ,  Naoyuki Eguchi ,  Hirofumi Sasaki

发明人： Hisakatsu Kato ,  Masashi Wada ,  Naoyuki Eguchi ,  Hirofumi Sasaki

IPC分类号： C01F7/14 ,  B01J8/10

CPC分类号： B01F7/00208 ,  B01F7/00641 ,  B01F7/1675 ,  B01F7/22 ,  B01F15/00837 ,  B01F2215/0431 ,  B01F2215/044 ,  B01F2215/0472 ,  B01F2215/0477 ,  B01J19/006 ,  B01J19/0066 ,  B01J19/1812 ,  B01J2219/00768 ,  C01F7/02 ,  C01F7/14 ,  C01F7/144 ,  C01F7/147 ,  C01P2004/50 ,  C01P2004/61 ,  C01P2006/60 ,  C09C1/407 ,  Y10T428/2982

摘要： Aluminum hydroxide aggregated particles which have an average particle diameter of not less than 40 μm, an average particle diameter as determined after pressing at 1,000 kg/cm2 of not more than 35 μm, and an L value of slurry obtained by mixing 20 ml of glycerol and 10 g of the aluminum hydroxide aggregated particles of not more than 69, are obtained by a process comprising the steps of: (a) feeding a supersaturated aqueous sodium aluminate solution to a vessel, (b) adding aluminum hydroxide seeds to the supersaturated aqueous sodium aluminate solution, (c) stirring the seed-added solution in the vessel while continuously feeding an additional supersaturated aqueous sodium aluminate solution into the vessel to hydrolyze the supersaturated aqueous sodium aluminate solution, (d) separating the aluminum hydroxide aggregated particles from the aqueous sodium aluminate solution, and (e) continuously discharging the aqueous sodium aluminate solution out of the vessel.

摘要翻译： 平均粒径为40μm以上的氢氧化铝凝集粒子，1000kg / cm 2以上压制后测定的平均粒径为35μm以下，通过将20ml甘油 和10g不超过69的氢氧化铝凝集颗粒，通过包括以下步骤的方法获得：（a）将过饱和的铝酸钠水溶液进料到容器中，（b）将氢氧化铝种子加入到过饱和水溶液 铝酸钠溶液，（c）在容器中搅拌添加种子的溶液，同时连续向容器中加入过饱和的铝酸钠水溶液以水解过饱和的铝酸钠水溶液，（d）将氢氧化铝凝集颗粒与水溶液 铝酸钠溶液，和（e）将铝酸钠水溶液连续排出容器。

公开(公告)号：US06016560A

公开(公告)日：2000-01-18

申请号：US981094

申请日：1998-03-17

申请人： Masashi Wada ,  Takao Okuba ,  Takeshi Furuno

发明人： Masashi Wada ,  Takao Okuba ,  Takeshi Furuno

IPC分类号： G11C29/00 ,  G01R31/28 ,  G11C7/00

CPC分类号： G11C29/70 ,  G11C29/88

摘要： A semiconductor memory (1), having a plurality of memory blocks (2 and 3) provided with a plurality of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating defective memory blocks and detection means (32) for detecting an access to a defective memory block designated by the first storage means in accordance with an address signal. When the detection means detects an access to a defective memory, the first control means inhibits the data rewrite operation for an instruction for a data rewrite operation and inhibits the output of data from the input/output buffer for the data read operation. The inhibiting function makes it possible to provide a memory device having compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.

摘要翻译： PCT No.PCT / JP96 / 01447 Sec。 371日期：1998年3月17日 102（e）1998年3月17日PCT PCT 1996年5月29日PCT公布。 出版物WO97 / 00518 日期1997年1月3日具有设置有多个存储单元的多个存储块（2和3），数据输入/输出缓冲器（7）和控制装置（11）的半导体存储器（1） 提供存储单元的数据的重写和读取用于指定缺陷存储块的第一存储装置（30）和用于根据地址检测对由第一存储装置指定的缺陷存储块的访问的检测装置（32） 信号。 当检测装置检测到对缺陷存储器的访问时，第一控制装置禁止用于数据重写操作的指令的数据重写操作，并且禁止用于数据读取操作的来自输入/输出缓冲器的数据的输出。 抑制功能使得可以仅通过组合具有不可弥补缺陷的半导体存储器来提供具有与无缺陷半导体存储器的兼容性的存储器件，而不固定特定地址输入端子的电平，以便保持有缺陷的存储块非选择性。

公开(公告)号：US5847995A

公开(公告)日：1998-12-08

申请号：US852354

申请日：1997-05-07

申请人： Shinichi Kobayashi ,  Shinji Kawai ,  Tadashi Omae ,  Makoto Oi ,  Akinori Matsuo ,  Masashi Wada ,  Kenji Kozakai

发明人： Shinichi Kobayashi ,  Shinji Kawai ,  Tadashi Omae ,  Makoto Oi ,  Akinori Matsuo ,  Masashi Wada ,  Kenji Kozakai

IPC分类号： G11C17/00 ,  G11C16/06 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/78

摘要： The inventive DINOR flash memory includes a plurality of blocks, a spare block and a spare word line block, which are formed on a plurality of electrically isolated P-type wells. When a word line-to-well short-circuit takes place in a certain block and another block is selected, the block causing the word line-to-well short-circuit is brought into a non-selected state. Thus, no leakage takes place in the block causing the word line-to-well short-circuit, to exert no bad influence on the selected block.

摘要翻译： 本发明的DINOR闪速存储器包括形成在多个电隔离P型阱上的多个块，备用块和备用字线块。 当在某个块中发生字线对阱短路并且选择另一个块时，导致字线对阱短路的块被带入非选择状态。 因此，在导致字线到阱短路的块中不发生泄漏，对所选择的块不会产生不良影响。

公开(公告)号：US5521417A

公开(公告)日：1996-05-28

申请号：US332377

申请日：1993-01-19

申请人： Masashi Wada

发明人： Masashi Wada

IPC分类号： H01L27/00 ,  H01L21/82 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/11507 ,  H01L27/112 ,  H01L27/11293 ,  H01L27/11502

摘要： A semiconductor device with a non-volatile memory on a data processing block, having a semiconductor substrate (100); a data processing block (202) having active elements for performing data processing and formed directly on the semiconductor substrate (100); and a memory block (206, 302) for previously storing information necessary for performing the data processing. The passive memory cell array (302) is formed above the active data processing block (202) and the active peripheral circuit (206), with an insulating passivation film (110) interposed therebetween. The memory block includes a memory cell array (302) having a plurality of memory cells as passive elements and a peripheral circuit (206) having active elements for reading data from the memory cell array. The memory cell array (302) has a plurality of conductors (112) in the X direction and conductors (115) in the Y direction, respectively to be selected by the peripheral circuit (206). The X and Y direction conductors (112, 115) are formed as two upper and lower layers with an insulating film (113 ) interposed therebetween. The X and Y direction conductors are three-dimensionally intersected to form the memory cells.

摘要翻译： 一种在数据处理块上具有非易失性存储器的半导体器件，具有半导体衬底（100）; 具有用于执行数据处理并且直接形成在半导体衬底上的有源元件的数据处理块（202）; 以及用于预先存储执行数据处理所需的信息的存储块（206,302）。 无源存储单元阵列（302）形成在有源数据处理块（202）和有源外围电路（206）之上，绝缘钝化膜（110）插入其间。 存储块包括具有作为无源元件的多个存储单元的存储单元阵列（302）和具有用于从存储单元阵列读取数据的有源元件的外围电路（206）。 存储单元阵列（302）分别在X方向上具有多个导体（112），并且在Y方向上分别具有由外围电路（206）选择的导体（115）。 X和Y方向导体（112,115）形成为隔着绝缘膜（113）的两个上下层。 X和Y方向导体三维相交以形成存储单元。

公开(公告)号：US5262985A

公开(公告)日：1993-11-16

申请号：US659183

申请日：1991-02-22

申请人： Masashi Wada

发明人： Masashi Wada

IPC分类号： G11C16/16 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  G11C16/00 ,  G11C16/06

CPC分类号： H01L27/11526 ,  G11C16/16 ,  H01L27/11546

摘要： A nonvolatile semiconductor memory device according to the present invention comprises a memory cell array composed of a collection of blocks, each block containing memory cells sharing the source or drain, a first region having the memory cell array formed in its surface region, and a control circuit that, in the erase mode, sets the source shared by a plurality of memory cells to be erased in one block at a first potential and the first region at a second potential higher than the GND potential and lower than the first potential, and at the same time, sets the source shared by a plurality of memory cells not to be erased in other blocks at a third potential equal to or higher than the second potential and lower than the first potential.

公开(公告)号：US4990980A

公开(公告)日：1991-02-05

申请号：US390510

申请日：1989-08-07

申请人： Masashi Wada

发明人： Masashi Wada

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/06 ,  H01L29/78 ,  H01L29/94

CPC分类号： H01L27/10864 ,  H01L27/10841 ,  H01L29/0692 ,  H01L29/7827 ,  H01L29/945

摘要： Island layers defined by grooves are formed on a p.sup.+ -type silicon substrate. One memory cell having a MOS capacitor and a MOSFET transistor is formed in each island layer. The MOS capacitor is buried in a groove surrounding the island layer and has a capacitor electrode insulatively provided over the bottom surface of the groove and an n.sup.- -type semiconductor layer formed in a ring-shaped manner in the side surface region of the groove and facing the capacitor electrode. The MOSFET has a ring-shaped gate electrode for in the groove to be insulatively stacked over the capacitor electrode. The gate electrode faces a p-type channel region formed in a ring-shaped manner in the side surface region of the island layer. Only a drain layer is formed in the top surface region of the island layer.

摘要翻译： 由p +型硅衬底形成由沟槽限定的岛层。 在每个岛层形成具有MOS电容器和MOSFET晶体管的一个存储单元。 MOS电容器被埋在围绕岛层的沟槽中，并且具有绝缘地设置在沟槽的底表面上的电容器电极和在槽的侧表面区域以环状形成的n型半导体层， 面对电容器电极。 MOSFET具有用于凹槽中的环形栅电极，绝缘层叠在电容器电极上。 栅极电极面对在岛状层的侧面区域中以环状形成的p型沟道区域。 在岛层的顶面区域仅形成漏极层。