摘要:
A semiconductor memory (1), having a plurality of memory blocks (2 and 3) provided with a plurality of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating defective memory blocks and detection means (32) for detecting an access to a defective memory block designated by the first storage means in accordance with an address signal. When the detection means detects an access to a defective memory, the first control means inhibits the data rewrite operation for an instruction for a data rewrite operation and inhibits the output of data from the input/output buffer for the data read operation. The inhibiting function makes it possible to provide a memory device having compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.
摘要:
A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data-input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.
摘要:
A memory apparatus packaged in one package is provided which includes first data terminals, first address terminals, a status terminal, and memory chips integrated in one semiconductor substrate, one of the memory chips being a nonvolatile memory. Each of the memory chips includes data terminals and address terminals. The data terminals of each of the memory chips are connected to the first data terminals, and the address terminals of each of the memory chips are connected to the first address terminals. The status terminal is arranged to output a status signal which indicates when the nonvolatile memory is in a ready status or in a busy status.
摘要:
A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by a ejecting an electric charge accumulated at floating gates by program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.
摘要:
A semiconductor memory (1) comprising a plurality of memory blocks (2 and 3) provided with a lot of memory cells, a data input/output buffer (7), and first control means (11) for controlling the rewriting and reading of data for the memory cells is provided with first storage means (30) for designating part of the defective memory blocks and detection means (32) for detecting the access to a defective memory block designated by the first storage means in accordance with an address signal. In this case, when the detection means detects the access to a defective memory, the first control means inhibits the data rewrite operation for the instruction of the data rewrite operation and inhibits the data output operation of the data input/output buffer for the instruction of the data read operation. The inhibiting function makes it possible to provide a memory device having the compatibility with a non-defective semiconductor memory only by combining semiconductor memories having irremediable defects without fixing the levels of specific address input terminals so as to keep the defective memory blocks non-selective.
摘要:
A batch erasable single chip nonvolatile memory device and a method therefor of using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation) carries out, in sequence a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltages, or is provided with an automatic erasing circuit for executing these operations.
摘要:
A batch erasable nonvolatile memory device and an apparatus using the same provided with memory cells which are adapted to execute an erase operation by ejecting an electric charge, accumulated at floating gates by a program operation (including a pre-write operation), carries out, in sequence, a first operation for reading memory cells of an erase unit and carrying out a pre-write operation on those nonvolatile memory cells at the floating gates of which electric charge is not stored, a second operation for carrying out a batch erase operation at a high speed for the nonvolatile memory cells of said erase unit with a relatively large energy under a relatively large erase reference voltage, a third operation for carrying out a read operation of said all erased nonvolatile memory cells and a write operation on those nonvolatile memory cells which are adapted to have a relatively low threshold voltage, and a fourth operation for carrying out a batch erase operation at a low speed for the nonvolatile memory cells of said erase unit with a relatively small energy under a relatively small erase reference voltage, or is provided with an automatic erasing circuit for executing these operations.
摘要:
Two paths for receiving the outputs of a logic select circuit LOGS are individually equipped in a symmetric manner with output MOSFETs Q52 and Q53, feedback MOSFETs Q54 and Q55 and isolating MOSFETs Q56 and Q57, the paired of which have conduction types different from each other. Negative erasing Vee voltage and programming Vpp voltage to be fed to the paths through the feedback MOSFETs are prevented without fail from being transmitted to a logic select circuit by the paired isolating MOSFETs of the different conduction types. As the elements for selecting the positive or negative logic output of the logic select circuit, CMOS transfer gates TG1 and TG2 can be adopted to maximize the amplitude of the output logic signal of the logic select circuit with respect to an operating power.
摘要:
Aluminum hydroxide aggregated particles which have an average particle diameter of not less than 40 μm, an average particle diameter as determined after pressing at 1,000 kg/cm2 of not more than 35 μm, and an L value of slurry obtained by mixing 20 ml of glycerol and 10 g of the aluminum hydroxide aggregated particles of not more than 69, are obtained by a process comprising the steps of: (a) feeding a supersaturated aqueous sodium aluminate solution to a vessel, (b) adding aluminum hydroxide seeds to the supersaturated aqueous sodium aluminate solution, (c) stirring the seed-added solution in the vessel while continuously feeding an additional supersaturated aqueous sodium aluminate solution into the vessel to hydrolyze the supersaturated aqueous sodium aluminate solution, (d) separating the aluminum hydroxide aggregated particles from the aqueous sodium aluminate solution, and (e) continuously discharging the aqueous sodium aluminate solution out of the vessel.
摘要翻译:平均粒径为40μm以上的氢氧化铝凝集粒子,1000kg / cm 2以上压制后测定的平均粒径为35μm以下,通过将20ml甘油 和10g不超过69的氢氧化铝凝集颗粒,通过包括以下步骤的方法获得:(a)将过饱和的铝酸钠水溶液进料到容器中,(b)将氢氧化铝种子加入到过饱和水溶液 铝酸钠溶液,(c)在容器中搅拌添加种子的溶液,同时连续向容器中加入过饱和的铝酸钠水溶液以水解过饱和的铝酸钠水溶液,(d)将氢氧化铝凝集颗粒与水溶液 铝酸钠溶液,和(e)将铝酸钠水溶液连续排出容器。
摘要:
A pair of seat backs are arranged in a vehicle width direction. A pair of floor brackets attach outer end portions of the seat backs in the vehicle width direction to a floor of the vehicle. A pair of center hinge brackets attach inner end portions of the seat backs in the vehicle width direction to the floor. A supporting bar is separated from the floor, is extended in the vehicle width direction and is disposed behind the seat backs. The seat backs are independently pivotably attached to the floor. Both end portions of the supporting bar in the vehicle width direction are attached to the floor brackets. A center portion of the supporting bar in the vehicle width direction is attached to the center hinge brackets.