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    Semiconductor device and manufacturing method thereof
    4.
    发明授权
    Semiconductor device and manufacturing method thereof 失效
    半导体装置及其制造方法

    公开(公告)号：US06518635B1

    公开(公告)日：2003-02-11

    申请号：US09610862

    申请日：2000-07-06

    申请人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Yuji Abe ,  Yasunori Tokuda

    发明人： Katsuomi Shiozawa ,  Toshiyuki Oishi ,  Yuji Abe ,  Yasunori Tokuda

    IPC分类号： H01L27108

    CPC分类号： H01L29/517 ,  H01L21/26506 ,  H01L21/26586 ,  H01L21/28167

    摘要： A major object of the present invention is to provide an improved semiconductor device so as to be able to reduce gate electric field concentration at a channel edge, suppress decrease in the threshold during MOSFET operation and reduce the leakage current. A gate insulation film is formed on a semiconductor substrate. A gate electrode is formed on the semiconductor substrate with the gate insulation film therebetween. The dielectric constant of the gate insulation film is not uniform in the surface.

    摘要翻译： 本发明的主要目的是提供一种改进的半导体器件，以便能够降低沟道边缘处的栅极电场集中，抑制MOSFET操作期间阈值的降低并减少漏电流。 在半导体衬底上形成栅极绝缘膜。 栅电极形成在半导体衬底上，其间具有栅极绝缘膜。 栅极绝缘膜的介电常数在表面上不均匀。

    Method of making field effect transistor in which the increase of parasitic capacitance is restrained by scale reduction
    5.
    发明授权
    Method of making field effect transistor in which the increase of parasitic capacitance is restrained by scale reduction 失效
    制造场效应晶体管的方法，其中寄生电容的增加受缩小的限制

    公开(公告)号：US06624034B2

    公开(公告)日：2003-09-23

    申请号：US10173835

    申请日：2002-06-19

    申请人： Yuji Abe ,  Naruhisa Miura ,  Kohei Sugihara ,  Toshiyuki Oishi ,  Yasunori Tokuda

    发明人： Yuji Abe ,  Naruhisa Miura ,  Kohei Sugihara ,  Toshiyuki Oishi ,  Yasunori Tokuda

    IPC分类号： H01L21336

    CPC分类号： H01L29/6653 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/665 ,  H01L29/66628

    摘要： A method of producing a semiconductor device includes forming a gate electrode on a channel region on a surface of a semiconductor region of a semiconductor substrate, the channel region having a depth in the semiconductor substrate; forming a first pair of side wall spacers on opposite sides of the gate electrode; forming elevated semiconductor layers, each elevated semiconductor layer being elevated relative to the channel region, on regions outside of the pair of side wall spacers and in which source and drain regions of a first conductivity type are to be formed; removing the pair of first side wall spacers; and forming a pair of pocket injection regions of a second conductivity type by introducing, after the side wall spacers are removed, a dopant impurity producing the second conductivity type deeper in the semiconductor substrate than a region where the side wall spacers were formed, the pair of pocket injection regions respectively covering only a neighborhood of respective side surface parts of the channel region, where the source and drain regions are to be formed, forming respective pn junctions only between the neighborhood of the side surface parts and the pocket injection regions.

    摘要翻译： 一种制造半导体器件的方法包括在半导体衬底的半导体区域的表面上的沟道区上形成栅电极，所述沟道区在半导体衬底中具有深度; 在栅电极的相对侧上形成第一对侧壁间隔物; 形成升高的半导体层，每个升高的半导体层相对于沟道区域升高，在一对侧壁间隔物外侧的区域上，并且将形成第一导电类型的源极和漏极区域; 移除所述一对第一侧壁间隔件; 以及形成第二导电类型的一对口袋注入区域，在除去侧壁间隔物之后，在半导体衬底中产生比形成侧壁间隔物的区域更深的第二导电类型的掺杂剂杂质，该对 分别仅覆盖要形成源极和漏极区的沟道区的各个侧表面部分的附近的口腔注入区域，仅在侧表面部分的附近和口袋注入区域之间形成相应的pn结。

    Semiconductor device with sidewall spacers and elevated source/drain region
    6.
    发明授权
    Semiconductor device with sidewall spacers and elevated source/drain region 失效
    具有侧壁间隔件和升高的源极/漏极区域的半导体器件

    公开(公告)号：US06617654B2

    公开(公告)日：2003-09-09

    申请号：US09955488

    申请日：2001-09-19

    申请人： Toshiyuki Oishi ,  Kohei Sugihara ,  Naruhisa Miura ,  Yuji Abe ,  Yasunori Tokuda

    发明人： Toshiyuki Oishi ,  Kohei Sugihara ,  Naruhisa Miura ,  Yuji Abe ,  Yasunori Tokuda

    IPC分类号： H01L2976

    CPC分类号： H01L29/66628 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7834

    摘要： Source and drain regions include regions of an epitaxial silicon film on the surface of the substrate and regions in the substrate. The depth of junctions of the source and drain regions is identical to or shallower than the depth of junctions of extension regions. As a result, even if the thickness of the side wall layer is reduced, since the depletion layer of the extension regions with lower impurity concentration compared with the source and drain regions is predominant, the short channel effect has a smaller effect.

    摘要翻译： 源区和漏区包括在衬底的表面上的外延硅膜的区域和衬底中的区域。 源极和漏极区域的结的深度与延伸区域的接合点的深度相同或更浅。 结果，即使侧壁层的厚度减小，由于与源极和漏极区域相比，杂质浓度较低的延伸区域的耗尽层是主要的，所以短沟道效应具有较小的效果。

    Semiconductor device
    7.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US06566734B2

    公开(公告)日：2003-05-20

    申请号：US09809211

    申请日：2001-03-16

    申请人： Kohei Sugihara ,  Toshiyuki Oishi ,  Naruhisa Miura ,  Yuji Abe ,  Yasunori Tokuda

    发明人： Kohei Sugihara ,  Toshiyuki Oishi ,  Naruhisa Miura ,  Yuji Abe ,  Yasunori Tokuda

    IPC分类号： H01L29788

    CPC分类号： H01L29/66651 ,  H01L29/1045 ,  H01L29/1054 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66621

    摘要： In making a field effect transistor, a dummy gate electrode is formed before a gate electrode is formed. Extension regions, a side wall silicon nitride film, source/drain regions, a silicon oxide film, and other elements are formed with respect to the dummy gate electrode. The dummy gate electrode is removed, and a part of the extension regions diffused into a region immediately under the dummy gate electrode is removed. The removed part is filled with silicon selection epitaxial film. Thereafter, the intended gate electrode is formed. This production method produces a field effect transistor that prevents deterioration of electrical characteristics caused by the short channel effect and parasitic resistance.

    摘要翻译： 在制作场效应晶体管时，在形成栅电极之前形成伪栅电极。 相对于虚拟栅电极形成延伸区域，侧壁氮化硅膜，源极/漏极区域，氧化硅膜等元件。 去除虚拟栅电极，并且去除扩散到虚拟栅电极正下方的区域中的一部分延伸区域。 被去除的部分填充硅选择外延膜。 之后，形成预定的栅电极。 该制造方法产生场效应晶体管，其防止由短沟道效应和寄生电阻引起的电特性的劣化。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    9.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20090142871A1

    公开(公告)日：2009-06-04

    申请号：US12323634

    申请日：2008-11-26

    申请人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yosuke Suzuki ,  Katsuomi Shiozawa ,  Kyozo Kanamoto ,  Toshiyuki Oishi ,  Yasunori Tokuda ,  Tatsuo Omori

    发明人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yosuke Suzuki ,  Katsuomi Shiozawa ,  Kyozo Kanamoto ,  Toshiyuki Oishi ,  Yasunori Tokuda ,  Tatsuo Omori

    IPC分类号： H01L21/20 ,  H01L33/00

    CPC分类号： H01S5/34333 ,  B82Y20/00 ,  H01L33/325 ,  H01L33/40 ,  H01S5/0421 ,  H01S5/0425 ,  H01S5/22 ,  H01S5/2214 ,  H01S5/3063

    摘要： A method of manufacturing a semiconductor device provides a semiconductor device with a gallium-nitride-based semiconductor structure that allows long-term stable operation without degradation in device performance. After formation of an insulation film on a surface other than on a ridge surface, an oxygen-containing gas such as O2, O3, NO, N2O, or NO2 is supplied to oxidize a p-type GaN contact layer from the surface and to thereby form an oxide film on the surface of the p-type GaN contact layer. Then, a p-type electrode that establishes contact with the p-type GaN contact layer is formed by evaporation or sputtering on the oxide film and on the insulation film. Heat treatment is subsequently performed at temperatures between 400 and 700° C. in an atmosphere containing a nitrogen-containing gas such as N2 or NH3 or an inert gas such as Ar or He.

    摘要翻译： 半导体器件的制造方法为半导体器件提供了氮化镓基半导体结构，其允许长期稳定的操作而不会降低器件性能。 在表面以外的表面上形成绝缘膜之后，供给诸如O 2，O 3，NO，N 2 O或NO 2的含氧气体以从表面氧化p型GaN接触层，由此 在p型GaN接触层的表面上形成氧化膜。 然后，通过在氧化物膜和绝缘膜上的蒸发或溅射形成与p型GaN接触层建立接触的p型电极。 随后在含有含氮气体如N 2或NH 3或惰性气体例如Ar或He的气氛中，在400-700℃的温度下进行热处理。